K7R640982M Samsung semiconductor, K7R640982M Datasheet - Page 5

• Manufacturer Part Number: K7R640982M
• Description: 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM
• Manufacturer: Samsung semiconductor

K7R321884M
GENERAL DESCRIPTION
Read Operations
K7R323684M
The K7R323684M and K7R321884M are37,748,736-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7R323684M and 2,097,152 words by 18 bits for K7R321884M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address for read and write are latched on alternate rising edges of the input clock K.
Data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 4-bit sequential for both read and write operations, reguiring tow full clock bus cycles.
Any request that attempts to interrupt a burst operation in progress is ignored.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
Nybble write operation is supported with NW
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7R323684M and K7R321884M are implemented with SAMSUNG's high performance 6T CMOS technology
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 4-bit burst DDR operation, it will access four 36-bit or 18-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
The process continues until all four data are transfered.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the R is disabled after a read operation,the K7R323684M and K7R321884M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K , and transfered out of sram on every rising edge of C and C.
the data outputs are synchronized to the input clocks ( K and K ).
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
0
and BW
0
and NW
1
( BW
1
pins for x8 device.
2
and B W
- 5 -
1Mx36 & 2Mx18 QDR
3 )
pins.
TM
II b4 SRAM
Dec. 2003
Rev 2.0