AM29DL800B AMD [Advanced Micro Devices], AM29DL800B Datasheet

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... PRELIMINARY Am29DL800B 8 Megabit ( 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS Simultaneous Read/Write operations — Host system can program or erase in one bank, then immediately and simultaneously read from the other bank — Zero latency between read and write operations — ...

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... GENERAL DESCRIPTION The Am29DL800B Mbit, 3.0 volt-only flash memory device, organized as 524,288 words or 1,048,576 bytes. The device is offered in 44-pin SO, 48-pin TSOP, and 48-ball FBGA packages. The word- wide (x16) data appears on DQ0–DQ15; the byte-wide (x8) data appears on DQ0–DQ7. This device requires only a single 3 ...

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... REGISTER BYTE# DQ0–DQ15 A0–A18 2.7 – 3 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address Am29DL800B Am29DL800B 70 90 120 70 90 120 70 90 120 OE# BYTE# DQ0–DQ15 OE# BYTE# 21519A-1 ...

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... CC DQ11 13 DQ3 14 DQ10 15 DQ2 16 DQ9 17 DQ1 18 DQ8 19 DQ0 Standard TSOP Reverse TSOP Am29DL800B 48 A16 47 BYTE DQ15/A-1 44 DQ7 43 DQ14 42 DQ6 41 DQ13 40 DQ5 39 DQ12 38 DQ4 DQ11 35 DQ3 ...

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... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am29DL800B 44 RESET# 43 WE# 42 ...

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... V CC (see Product Selector Guide for speed options and voltage supply tolerances Device Ground Pin Not Connected Internally LOGIC SYMBOL 19 A0–A18 CE# OE# WE# RESET# BYTE# Am29DL800B DQ0–DQ15 (A-1) RY/BY# 21519A-4 ...

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... Valid Combinations Am29DL800BT70 EC, EI, FC, FI, Am29DL800BB70 SC, SI, WBC, WBI Am29DL800BT90 EC, EI, EE, Am29DL800BB90 FC, FI, FE, SC, SI, SE, Am29DL800BT120 WBC, WBI, WBE Am29DL800BB120 OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0°C to +70° Industrial (– ...

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... The command register it- self does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of Table 1. Am29DL800B Device Bus Operations Operation CE# Read L ...

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... CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I Characteristics table represents the automatic sleep mode current specification. Am29DL800B 0 but not within IH ) for read access when the ...

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... Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input disabled. The output pins are placed in the high imped- ance state. Am29DL800B (during Embedded Algorithms). The (not during Embedded Algo- READY after the RE- RH ...

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... Bank 1 SA18 SA19 SA20 SA21 Note: The address range is A18:A byte mode (BYTE Am29DL800BT Top Boot Sector Architecture Sector Size (Kbytes/ A15 A14 A13 A12 Kwords 64/ 64/32 0 ...

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... When using programming equipment, the autoselect mode requires V (11 12 address pin ID A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection Am29DL800BB Bottom Boot Sector Architecture Sector Size (Kbytes/ A15 A14 A13 A12 Kwords) ...

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... Table 4. Am29DL800B Autoselect Codes (High Voltage Method) Description Mode CE# Manufacturer ID: AMD L Device ID: Word L Am29DL800B Byte L (Top Boot Block) Device ID: Word L Am29DL800B Byte L (Bottom Boot Block) Sector Protection Verification L Note Logic Low = Logic High = V IL Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector ...

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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am29DL800B START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...

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... If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in Erase Suspend). Am29DL800B is greater than initiate a write cycle, IH ...

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... To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command se- quence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to reading array data. Am29DL800B ...

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... WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from Am29DL800B 17 ...

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... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 5 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am29DL800B START Embedded Erase algorithm in progress Yes 21519A-8 ...

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... Table 5. Am29DL800B Command Definitions Command Sequence (Note 1) Addr Data Addr Data Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector Protect 4 Verify (Note 9) Byte ...

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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am29DL800B Yes No Yes Yes No ...

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... DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation still toggling, the device did not Am29DL800B 21 ...

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... DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last com- mand might not have been accepted. Table 6 shows the status of DQ3 relative to the other status bits. Program/Erase Am29DL800B ...

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... The device outputs array data if the system addresses a non-busy bank Table 6. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am29DL800B DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data ...

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... Operating ranges define those limits between which the func- tionality of the device is guaranteed +0.8 V –0.5 V –2 Figure 7. Maximum Negative SS Overshoot Waveform +2 +0 Figure 8. Maximum Positive Overshoot Waveform Am29DL800B 21519A- 21519A-12 ...

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... IH Word CE IL 3 4.0 mA min I = –2 min I = –100 µ min . IH Am29DL800B Min Typ Max Unit 1.0 µA 35 µA 1.0 µ 0.2 5 µA 0.2 5 µA 0.2 5 µ ...

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... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am29DL800B 3000 3500 4000 21519A-13 3 21519A-14 ...

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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 21519A-15 INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am29DL800B All Unit 1 TTL gate L 100 0.0–3 ...

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... CE Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 13. Read Operation Timings Am29DL800B Speed Options 70 90 120 Unit Min 70 80 120 Max 70 80 120 Max 70 80 120 Max Max ...

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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 14. Reset Timings Am29DL800B All Speed Options Unit 20 µs 500 ns 500 µ 21519A-18 29 ...

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... Data Output (DQ0–DQ7) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am29DL800B 90 120 Unit 120 ns Data Output (DQ0–DQ7) Address Input Data Output (DQ0–DQ14) 21519A-19 21519A-20 ...

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... Min Min Min Min Min Min Min Min Min Min Min Min Min Min Byte Typ Word Typ Typ Min Min Min Am29DL800B 70 90 120 Unit 70 90 120 ...

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... OUT Figure 17. Program Operation Timings 555h for chip erase WPH 55h 30h 10 for Chip Erase t BUSY Am29DL800B Read Status Data (last two cycles WHWH1 D Status OUT t RB 21519A- WHWH2 In Complete Progress t RB 21519A-22 ...

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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am29DL800B Valid PA Valid PA t CPH t CP Valid Valid In In CE# Controlled Write Cycles 21519A-23 VA High Z True Valid Data High Z True Valid Data ...

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... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 22. DQ2 vs. DQ6 Am29DL800B Valid Valid Data Status (stops toggling) 21519A-25 Erase Resume Erase Erase Complete Read 21519A-26 ...

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... V RESET VIDR CE# WE# RY/BY# Figure 23. Temporary Sector Unprotect Timing Diagram Min Min Min Program or Erase Command Sequence t RSP Am29DL800B All Speed Options Unit 500 ns 4 µs 4 µ VIDR t RRB 21519A-27 35 ...

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... CE# WE# OE# * For sector protect For sector unprotect Figure 24. Sector Protect/Unprotect Timing Diagram Valid* Valid* Verify 60h Sector Protect: 100 µs Sector Unprotect Am29DL800B Valid* 40h Status 21519A-28 ...

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... See the “Erase and Programming Performance” section for more information Min Min Min Min Min Min Min Min Min Min Byte Typ Word Typ Typ Am29DL800B 70 90 120 Unit 70 90 120 ...

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... for program SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase Am29DL800B PA DQ7# D OUT 21519A-29 ...

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... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT V IN Test Conditions Am29DL800B Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) , 1,000,000 cycles. Additionally, CC Min Max –1.0 V 12.5 V –1 1 +100 mA ...

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... TSR048—48-Pin Reverse TSOP (measured in millimeters) Pin 1 I. 1.20 MAX 0.25MM (0.0098") BSC * For reference only. BSC is an ANSI standard for Basic Space Centering 18.30 18.50 19.80 20.20 0° 5° 0.50 0. 18.30 18.50 19.80 20.20 0° 5° 0.50 0.70 Am29DL800B 0.95 1.05 11.90 12.10 0.50 BSC 0.05 0.15 16-038-TS48-2 0.08 TS 048 0.20 DT95 8-8-96 lv 0.10 0.21 0.95 1.05 11.90 12.10 0.50 BSC 0.05 0.15 SEATING PLANE 16-038-TS48 TSR048 0.08 DT95 0.20 8-8-96 lv ...

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... PHYSICAL DIMENSIONS (continued) FGB048 —48-ball Fine-Pitch Ball Grid Array (FBGA (measured in mm) DATUM B 0.025 CHAMFER INDEX 0.80 0.40 ± 0.08 (48x) 0. 0.25 0.45 DETAIL A 1.20 MAX 0. 8.80 9.20 5.80 6.20 DATUM A 5.60 BSC 0.40 0.40 0.20 Z DETAIL A Am29DL800B 0. 4.00 BSC 0.10 Z 16-038-FGB-2 EG137 12-2- ...

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... PHYSICAL DIMENSIONS (continued) SO 044—44-Pin Small Outline (measured in millimeters 1.27 NOM. TOP VIEW 28.00 28.40 2.17 2.45 0.35 0.50 SIDE VIEW 13.10 15.70 13.50 16.30 22 2.80 MAX. SEATING PLANE 0.10 0.35 Am29DL800B 0.10 0.21 0° 0.60 8° 1.00 END VIEW 16-038-SO44-2 SO 044 DF83 8-8-96 lv ...

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... REVISION SUMMARY FOR AM29DL800B Revision A+1 Reset Command Deleted last paragraph in section, which applied to RE- SET#, not the reset command. Revision A+2 Hardware Reset (RESET#) Added note to table, fixed references to note. Revision A+3 Global Removed references to the 80 ns speed option. Changed the 70R ns (V ± 5%) speed option to the ...