EVAL-AD1556 AD [Analog Devices], EVAL-AD1556 Datasheet - Page 2

• Manufacturer Part Number: EVAL-AD1556
• Description: Evaluation Board AD1555/1556 24-Bit ADC
• Manufacturer: AD [Analog Devices]

OPERATING THE EVAL-AD1555/56EB
out and tested to demonstrate the specific high dynamic
performance of the chip-set.
Figure 4 shows the schematics of the evaluation board.
The layout of the board is given in the next four figures :
Figure 5 shows the Top side silk-screen.
Figure 6 shows the Top layer.
Figure 7 shows the Bottom side silk-screen.
Figure 8 shows the Bottom layer.
The available test points are listed in Table I and a description
of each selectable jumper is listed in Table II. The component
list is provided in Table III.
Power Supplies and Grounding :
single +5V supply V
section, another +5V or +3.3V supply V
supply of AD1555 only and a +/-5V supply (SJ3) for the
analog section of AD1555.
sections: a DGND plane for the AD1556 and the digital
interface circuitry, a LGND plane for the digital section of
AD1555 and an analog AGND plane for the AD1555, its
analog input and external reference circuitry. To facilitate
grounding connections of test equipment and attain high
performance the board was designed with a good isolation
barrier between the AD1555 and the rest of the digital
functions. This isolation barrier is not required in applications
where the analog and digital ground are not tied together
externally. That is achieved using optocouplers and high
value resistors. The analog ground and AD1555 digital
ground can be tied together close to the AD1555 using JP2
which is the optimal configuration.
Analog inputs :
T
to be compatible with the PGA gain settings used as described
in the AD1555/AD1556 datasheet. The modulator section of
the AD1555 can be separately evaluated using the
PGA_MOD SMB plug.
The EVAL-AD1555/56EB is a two-layer board carefully laid
Fully differential signals could be applied on either A
Test Point
EVAL-AD1555/AD1556
The EVAL-AD1555/56EB has three power supply blocks: a
The evaluation board ground plane is separated into three
IN
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
inputs through SMB plugs. The analog input ranges have
TABLE I. EVAL-AD1555/56EB Test Points
cc
(SJ1) for the evaluation board digital
PRELIMINARY TECHNICAL DATA
Available Signal
REFIN (3V)
DGND ( FPGA )
DGND ( AD1556 )
CB0
CB1
CB2
CB3
CB4
MDATA
MCLKOUT
MFLG
L
(SJ2) for the digital
IN
and
– 2 –
RUNNING THE EVAL-AD1555/56EB SOFTWARE
Software Description :
The EVAL-AD1555/56EB comes with software for analyzing
the AD1555/AD1556 chip-set. This software allows compre-
hensive control and evaluation of the AD1555/AD1556 chip-
set or the AD1555 and the AD1556 separately. The front-
end PC software has only one screen shown in Figure 1. This
screen is partitioned into five windows which allows the user
to select the configuration, launch the sampling sequence,
perform computation on the output signal and display the
results. The choices for display are Time domain response,
Spectral response and histogram chart. Different measure-
ments as Dynamic range, equivalent input noise, Total
Harmonic Distortion (THD) and DC offset can be done.
Figure 1 describes the steps to follow for proper software
operation.
Software Installation :
The EVAL-AD1555/56EB software runs under Windows95.
It requires a minimum of 7MB hard-disk space available and a
display with a minimum resolution of 800 by 600. Due to the
real-time operation, it is recommended that other programs
be closed when using the EVAL-AD1555/56EB software.
The EVAL-AD1555/56EB software installation process is:
- Run Setup.exe using the EVAL-AD1555/56EB disk 1 and
follow the instructions. The files can be stored in any direc-
tory at the user convenience using the destination folder field.
The default folder is C:\Program Files\Ad1555_56.
- Run AD1555_56.exe to launch the software. It will open
the window in figure 1.
- If the window in figure 1 exceeds the actual screen, the
display resolution needs to be increased by opening
Start>Settings>Control Panel>Display then settings>
800*600 for desktop area >apply>OK.
Jumper
JP1
JP2
SW1
TABLE II. JUMPER DESCRIPTION
To get all the software functionality, SW1 should
be in the position where the identification dot on
the core of the switch is visible.
When SW1 is in the other position ( the switch
hole is hidden ), the AD1556 could be controlled
externally using the 50-pin connector P2. ( see
chapter using the EVAL-AD1555/56EB in
customized system for details ).
JP1 controls the input signal applied to the
AD1555 modulator input MODIN. In position A,
the PGA output is applied to MODIN. In
position B, the signal on PGA_MOD SMB plug is
applied to MODIN.
JP2 allows LGND and AGND to be tied together
close to the AD1555 which is generally the
preferred configuration.
Function
REV. PrD