EVAL-AD73422EB AD [Analog Devices], EVAL-AD73422EB Datasheet
EVAL-AD73422EB
Related parts for EVAL-AD73422EB
EVAL-AD73422EB Summary of contents
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FEATURES AFE PERFORMANCE Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 s Typ per ADC ...
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AD73422–SPECIFICATIONS Parameter AFE SECTION REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback Capacitance ANALOG GAIN TAP Gain ...
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Parameter DAC SPECIFICATIONS 2 Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing (0 dBm0) Single-Ended Differential Output Bias Voltage Absolute Gain Gain Tracking Error Signal to (Noise + Distortion dBm0 PGA = 6 dB Total Harmonic ...
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AD73422–SPECIFICATIONS Parameter DSP SECTION V Hi-Level Input Voltage IH V Hi-Level CLKIN Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level Output Voltage OL I Hi-Level Input Current IH I Lo-Level Input Current IL I ...
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POWER CONSUMPTION Conditions Typ AFE SECTION ADCs Only On 11.5 DACs Only On 20 ADCs and DACs On 24.5 ADCs and DACs and Input Amps On 30 ADCs and DACs and AGT On 29 All Sections On 37 REFCAP Only ...
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... Although the AD73422 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Model AD73422BB-80 AD73422BB-40 EVAL-AD73422EB 1 A IRQE/PF4 B IRQL0/PF5 C ...
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BGA Mnemonic Location Function VINP1 T2 Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Positive Input. VFBP1 T1 Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the ...
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AD73422 PBGA BALL CONFIGURATION DESCRIPTIONS (Continued) BGA Mnemonic Location Function IRQL0/ (Input) Level-Sensitive Interrupt Requests PF5 B1 (Input/Output) Programmable I/O Pin. IRQE/ (Input) Edge-Sensitive Interrupt Requests PF4 A1 (Input/Output) Programmable I/O Pin. PF3 H4 (Input/Output) Programmable I/O Pin During Normal ...
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ARCHITECTURE OVERVIEW The AD73422 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single pro- cessor cycle. The AD73422 assembly language uses an algebraic syntax ...
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AD73422 VFBN1 VINN1 ANALOG V LOOP- REF BACK VINP1 VFBP1 VOUTP1 +6/–15dB PGA VOUTN1 REFERENCE REFCAP REFOUT VFBN2 VINN2 ANALOG V REF LOOP- BACK VINP2 VFBP2 VOUTP2 +6/–15dB PGA VOUTN2 Figure 2. Functional Block Diagram of Analog Front End Section ...
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Table I. PGA Settings for the Encoder Channel IGS2 IGS1 IGS0 ADC Both ADCs consist of ...
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AD73422 Decimation Filter The digital filter used in the AD73422’s AFE section carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator, and secondly, it decimates the high frequency bitstream to ...
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Differential Output Amplifiers The decoder has a differential analog output pair (VOUTP and VOUTN). The output channel can be muted by setting the MUTE bit (CRD:7) in Control Register D. The output signal is dc-biased to the codec’s on-chip voltage ...
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AD73422 AMCLK (EXTERNAL) DMCLK (INTERNAL) AMCLK DIVIDER 3 SE RESET SERIAL PORT 1 (SPORT 1) SDIFS SDI SERIAL REGISTER CONTROL CONTROL CONTROL REGISTER REGISTER REGISTER CONTROL CONTROL REGISTER REGISTER 1G CONTROL REGISTER ...
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CRC through CRH are used to hold control settings for the ADC, DAC, Reference, Power Control and Gain Tap sections of the device not necessary that the contents of CRC through CRH on each codec ...
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AD73422 Control Frame Description Bit 15 Control/Data When set high, it ...
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AD73422 ...
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OPERATION Resetting the AD73422’s AFE The pin ARESET resets all the control registers. All registers are reset to zero indicating that the default SCLK rate (DMCLK/8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP ...
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AD73422 A description of a single device operating in mixed mode is detailed in Appendix B, while Appendix D details the initializa- tion and operation of a dual codec cascade operating in mixed mode. Note that it is not essential ...
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There may be some restrictions in cascade operation due to the number of devices configured in the cascade and the sampling rate and serial clock rate chosen. The following relationship details the restrictions in configuring a codec cascade. Number of ...
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AD73422 Efficient data transfer is achieved with the use of five internal buses: • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) ...
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Full Memory Mode Pins (Mode Pin # of Input/ Name(s) Pins Output Function A13 Address Output Pins for Program, Data, Byte and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte and ...
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AD73422 The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level- sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table XX. ...
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When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at ...
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AD73422 Reset The RESET signal initiates a master reset of the AD73422. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock ...
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MEMORY ARCHITECTURE The AD73422 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O. Refer to the following figures and tables for PM and DM memory alloca- tions ...
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AD73422 Table XXIV. Wait States Address Range Wait State Register 0x000–0x1FF IOWAIT0 0x200–0x3FF IOWAIT1 0x400–0x5FF IOWAIT2 0x600–0x7FF IOWAIT3 Composite Memory Select (CMS) The AD73422 has a programmable memory select signal that is useful for generating memory select signals for memories ...
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The BDMA Context Reset bit (BCR) controls whether or not the processor is held off while the BDMA accesses are occur- ring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 ...
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AD73422 Bus Request and Bus Grant (Full Memory Mode) The AD73422 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If ...
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The following pins are also used by the EZ-ICE RESET GND The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the AD73422 in the target system. This causes the pro- cessor to use its ...
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AD73422 TFS SDIFS DT SCLK SCLK DR DSP SDO SECTION RFS SDOFS ARESET FL0 FL1 Figure 22. AD73422 AFE to DSP Connection Cascade Operation Where it is required to configure extra analog I/O channels to the existing two channels on ...
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Analog Inputs There are several different ways in which the analog input (en- coder) section of the AD73422 can be interfaced to external circuitry. It provides optional input amplifiers which allows sources with high source impedance to drive the ADC ...
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AD73422 In the case of ac-coupling, a capacitor is used to couple the signal to the input of the ADC. The ADC input must be biased to the internal reference (REFCAP) level, which is done by connecting the input to ...
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ADC’s full-scale input range. The buffered internal reference level at REFOUT is used via an external ...
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AD73422 Grounding and Layout As the analog inputs to the AD73422’s AFE section are differ- ential, most of the voltages in the analog modulator are common- mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on ...