EVAL-AD73422EB AD [Analog Devices], EVAL-AD73422EB Datasheet - Page 33

• Manufacturer Part Number: EVAL-AD73422EB
• Description: Dual Low Power CMOS Analog Front End with DSP Microcomputer
• Manufacturer: AD [Analog Devices]

Analog Inputs
There are several different ways in which the analog input (en-
coder) section of the AD73422 can be interfaced to external
circuitry. It provides optional input amplifiers which allows
sources with high source impedance to drive the ADC section
correctly. When the input amplifiers are enabled, the input
channel is configured as a differential pair of inverting amplifiers
referenced to the internal reference (REFCAP) level. The in-
verting terminals of the input amplifier pair are designated as
pins VINP1 and VINN1 for Channel 1 (VINP2 and VINN2 for
Channel 2) and the amplifier feedback connections are available
on pins VFBP1 and VFBN1 for Channel 1 (VFBP2 and VFBN2
for Channel 2).
For applications where external signal buffering is required, the
input amplifiers can be bypassed and the ADC driven directly.
When the input amplifiers are disabled, the sigma-delta mod-
ulator’s input section (SC PGA) is accessed directly through the
VFBP1 and VFBN1 pins for Channel 1 (VFBP2 and VFBN2
for Channel 2).
It is also possible to drive the ADCs in either differential or
single-ended modes. If the single-ended mode is chosen it is
possible using software control to multiplex between two single-
ended inputs connected to the positive and negative input pins.
The primary concerns in interfacing to the ADC are firstly to
provide adequate antialias filtering and to ensure that the signal
source will correctly drive the switched-capacitor input of the
ADC. The sigma-delta design of the ADC and its oversampling
characteristics simplify the antialias requirements, but it must be
remembered that the single-pole RC filter is primarily intended
to eliminate aliasing of frequencies above the Nyquist fre-
quency of the sigma-delta modulator’s sampling rate (typi-
cally 2.048 MHz). It may still require a more specific digital
filter implementation in the DSP to provide the final signal
frequency response characteristics. It is recommended that for
optimum performance the capacitors used for the antialiasing
filter be of high quality dielectric (NPO). The second issue
mentioned above is interfacing the signal source to the ADC’s
switched capacitor input load. The SC input presents a complex
dynamic load to a signal source, so it is important to understand
that the slew rate characteristic is an important consideration
when choosing external buffers for use with the AD73422. The
internal inverting op amps on the AD73422’s AFE are specifi-
cally designed to interface to the ADC’s SC input stage.
The AD73422’s on-chip 38 dB preamplifier can be enabled
when there is not enough gain in the input circuit; the preampli-
fier is configured by bits IGS0–2 of CRD. The total gain must
be configured to ensure that a full-scale input signal produces a
signal level at the input to the sigma-delta modulator of the
ADC that does not exceed the maximum input range.
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased at
the internal reference level (via REFOUT), it must be ac-coupled
with external coupling capacitors. C
larger. The dc biasing of the input can then be accomplished
using resistors to REFOUT as in Figures 28 and 29.
REV. 0
IN
should be 0.1 µF or
–33–
The AD73422’s ADC inputs are biased about the internal refer-
ence level (REFCAP level), therefore it may be necessary to
either bias external signals to this level using the buffered
REFOUT level as the reference. This is applicable in either dc-
or ac-coupled configurations. In the case of dc-coupling, the
signal (biased to REFOUT) may be applied directly to the in-
puts (using amplifier bypass), as shown in Figure 25, or it may
be conditioned in an external op amp where it can also be bi-
ased to the reference level using the buffered REFOUT signal as
shown in Figure 26. It is also possible to connect inputs directly
to the AD73422’s input op amps as shown in Figure 27.
OPTIONAL
Figure 26. Analog Input (DC-Coupled) Using External
Amplifiers
BUFFER
Figure 27. Analog Input (DC-Coupled) Using Internal
Amplifiers
50k
50k
ANTIALIAS
FILTER
0.047 F
0.047 F
100pF
100
50k
100pF
100
50k
REFOUT
VOUTN1
REFCAP
VOUTP1
REFOUT
VOUTP1
VOUTN1
REFCAP
0.1 F
0.1 F
VFBN1
VINN1
VINP1
VFBP1
V
VFBN1
VINN1
VINP1
VFBP1
V
REF
REF
+6/–15dB
+6/–15dB
GAIN
PGA
GAIN
PGA
1
1
REFERENCE
REFERENCE
CONTINUOUS
CONTINUOUS
LOW-PASS
LOW-PASS
FILTER
TIME
FILTER
TIME
AD73422
AD73422
AD73422
V
V
REF
REF
0/38dB
0/38dB
PGA
PGA