EVAL-AD73422EB AD [Analog Devices], EVAL-AD73422EB Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD73422EB
• Description: Dual Low Power CMOS Analog Front End with DSP Microcomputer
• Manufacturer: AD [Analog Devices]

AD73422
Mnemonic
IRQL0/
PF5
IRQE/
PF4
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN
XTAL
CLKOUT
SPORT0
SPORT1
FL0
FL1
FL2
VDD(INT)
VDD(EXT)
GND
EZ-ICE Port
A
Data Bus
NOTES
1
2
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
SPORT configuration determined by the DSP System Control Register. Software configurable.
ddress Bus
TFS0
RFS0
DT0
DR0
SCLK0
TFS1/
IRQ1
RFS1
IRQ0
DT1/
FO
DR1/
FI
SCLK1
ERESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
EBR
EBG
BGA
Location
B1
A1
H4
G7
F7
F6
A4
B4
D4
E2
E3
E1
F1
F2
G1
G2
F3
G3
H1
H5
H6
H7
A3
N3
C4
G6
M5
C7
D5
G4
N5
H2
J1
J2
J3
K1
K2
K3
P1
M1
A0–E7; A1/IAD0–E6; A2/IAD1–E5; A3/IAD2–E4; A4/IAD3–A7; A5/IAD4–B7; A6/IAD5–D7; A7/IAD6–A6;
A8/IAD7–B6; A9/IAD8–C6; A10/IAD9–D6; A11/IAD10–A5; A12/IAD11–B5; A13/IAD12–C5
M4; D8–L4; D9–L5; D10–N6; D11–M6; D12–L6; D13–N7; D14–M7; D15–L7; D16–K7; D17–K6; D18–K5;
D19–K4; D20–J7; D21–J6; D22–J5; D23–J4
D0/IAD13–P2; D1/IAD14–N2; D2/IAD15–M2; D3/IACK–L2; D4/IS–M3; D5/IAL–L3; D6/IRD–N4; D7/IWR–
Function
(Input) Level-Sensitive Interrupt Requests
(Input/Output) Programmable I/O Pin.
(Input) Edge-Sensitive Interrupt Requests
(Input/Output) Programmable I/O Pin.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Input) Mode Select Input—Checked Only During RESET.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Input) Mode Select Input—Checked Only During RESET.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Input) Mode Select Input—Checked Only During RESET.
(Input/Output) Programmable I/O Pin During Normal Operation.
(Inputs) Clock or Quartz Crystal Input. The CLKIN input cannot be halted or changed during operation
nor operated below 10 MHz during normal operation.
(Output) Processor Clock Output.
(Input/Output) SPORT0 Transmit Frame Sync.
(Input/Output) SPORT0 Receive Frame Sync.
(Output) SPORT0 Transmit Data.
(Input) SPORT0 Receive Data.
(Input/Output) SPORT0 Serial Clock.
(Input/Output) SPORT1 Transmit Frame Sync.
(Input) Edge or Level Sensitive Interrupt.
(Input/Output) SPORT1 Receive Frame Sync.
(Input) Edge or Level Sensitive Interrupt.
(Output) SPORT1 Transmit Data.
(Output) Flag Out
(Input) SPORT1 Receive Data.
(Input) Flag In
(Input/Output) SPORT1 Serial Clock.
(Output) Flag 0.
(Output) Flag 1.
(Output) Flag 2.
(Input) DSP Core Supply.
(Input) DSP I/O Interface Supply.
DSP Ground.
PBGA BALL CONFIGURATION DESCRIPTIONS (Continued)
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1
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REV. 0