EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

Input
Mode
(S3)
Position 0
LJ-24 Bits
Input
Mode (S3) Mode (JP1) Mode (S4)
LJ
I
RJ-24
RJ-20
RJ-18
RJ-16
DEFAULT CONFIGURATION
The default configuration of this evaluation board is highlighted
in Tables VII and VIII. The AD1896 is configured in 24-bit
input and output data format, with input serial ports in slave
mode and output serial port in (768
configuration, input serial port needs to be driven by an external
system, such as, Audio Precision, for the slave mode operation.
An on-board third overtone crystal oscillator at 33.8688 MHz
clocks the AD1896. Since the output serial port is configured
in 768
33.8688 MHz clock, the output sample rate will be 44.1 kHz
for this configuration. The maximum input sample rate for this
case can be up to 192 kHz based on the requirement that the
AD1896 master clock must be higher than 138 times the
maximum input or output sample rate. The AD1896 can be
clocked by secondary on-board clock oscillator (U15) by first
inserting the desired clock oscillator in socket U15 and then
switching the clock source selection from on-board crystal to
clock oscillator (U15) by jumper JP4; however, clock oscillator is
2
S
X
f
S
master mode and the AD1896 is clocked by
Output
LJ-24
I
RJ-24
RJ-20
RJ-18
RJ-16
TDM
2
S-24
Output
Mode
(JP1)
Position 1, 2, 3, 4
Shorted
LJ-24 Bits
X Both Ports in
Master/Slave
SLAVE Mode
O_MAS_768
O_MAS_512
O_MAS_256
MATCHED
PHASE
I_MAS_768
I_MAS_512
I_MAS_256
Master/Slave
Mode
(S4)
Position 6
Output Port
Master,
768 f
f
Table VIII. Default Evaluation Board Configuration
S
) master mode. In this
X TDM_IN
S_OUT
Table VII. Default Jumper/Switch Settings
Input Source
(HDR3, HDR1,
J1, U4)
DIRECT
INPUT
SPDIF
TOSLINK
Group Delay
(S8)
Short
Long
DAC
Interpolation
(JP2)
Shorted
Sample
Rate
Ratio Select
Position 1, 2
48 kHz
X Enable
X SPDIF
Output Source
(HDR2, HDR5,
J2)
DIRECT
OUTPUT
TDM_OUT
Bypass Mode
(S6)
Disable
enabled for SLAVE mode only (Switch S3 position 7). The evalua-
tion board contains 12.288 MHz (U15) clock oscillator. The
operating and quiescent currents for the ± 12 V dc supplies are
listed below.
+12 V Quiescent Current
–12 V Quiescent Current
+12 V Normal Operation Current
–12 V Normal Operation Current
AP1 TRANSMITTER
Clock
Source
(JP4)
Position 2, 3
Shorted
33.8688 MHz
Crystal
Oscillator
LRCLK
SDATA
SCLK
X
X
DAC
Interpolation
Ratio Select
(JP2)
96/48
192/48
Automute
Enable (JP3)
Enable
Disable
SCLK_I
LRCLK_I
SDATA_I
Group
Delay
(S8)
Pushed Up
Short
AD1896
X On-Board
X External
X Enable
LRCLK_O
SDATA_O
EVAL-AD1896EB
SCLK_O
Clock Source
(JP4)
33.8688 MHz Crystal
256
Mute
(S7)
Disable
Bypass
Mode
(S6)
Down
Off
Pushed
~250 mA
~5 mA
~300 mA–360 mA
~5 mA
f
S
Clock
AP2 RECEIVER
SCLK
LRCLK
SDATA
Mute
(S7)
Pushed
Down
Off
X
X