CS5532ASZ Cirrus Logic, Inc., CS5532ASZ Datasheet

CS5532ASZ

Manufacturer Part Number

CS5532ASZ

Description

SSOP20

Manufacturer

Cirrus Logic, Inc.

Datasheet

1.CS5532ASZ.pdf (51 pages)

Specifications of CS5532ASZ

Date_code

08+

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Features

Preliminary Product Information

http://www.cirrus.com

Chopper-stabilized PGIA (Programmable

Gain Instrumentation Amplifier, 1x to 64x)

Delta-sigma Analog-to-digital Converter

Two- or Four-channel Differential MUX

Scalable Input Span via Calibration

Scalable V

Simple Three-wire Serial Interface

R/W Calibration Registers Per Channel

Selectable Word Rates: 6.25 to 3,840 Sps

Selectable 50 or 60 Hz Rejection

Power Supply Configurations

6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x

500 pA Input Current with Gains >1

Linearity Error: 0.0007% FS

Noise Free Resolution: Up to 23 bits

±5 mV to differential ±2.5V

SPI™ and Microwire™ Compatible

Schmitt Trigger on Serial Clock (SCLK)

VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V

VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V

VA+ = +3 V; VA- = -3 V; VD+ = +3 V

16-bit and 24-bit ADCs

AIN1+

AIN2+

AIN3+

AIN4+

AIN1-

AIN2-

AIN3-

AIN4-

REF

Input: Up to Analog Supply

VA+

VA-

(CS5533/34

SHOWN)

MUX

PGIA

1,2,4,8,16

32,64

A0/GUARD

LATCH

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

VREF+

DIFFERENTIAL

MODULATOR

ORDER ∆Σ

with

VREF-

General Description

The CS5531/32/33/34 are highly integrated ∆Σ Analog-

to-Digital Converters (ADCs) which use charge-balance

techniques to achieve 16-bit (CS5531/33) and 24-bit

(CS5532/34) performance. The ADCs are optimized for

measuring low-level unipolar or bipolar signals in weigh

scale,

applications.

To accommodate these applications, the ADCs come as

either

(CS5533/34) devices and include a very low noise chop-

per-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1

Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and

64×. These ADCs also include a fourth order ∆Σ modu-

lator followed by a digital filter which provides twenty

selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,

50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,

1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).

To ease communication between the ADCs and a micro-

controller, the converters include a simple three-wire se-

rial interface which is SPI and Microwire compatible with

a Schmitt Trigger input on the serial clock (SCLK).

High dynamic range, programmable output rates, and

flexible power supply options makes these ADCs ideal

solutions

applications.

ORDERING INFORMATION

See page 48

Ultra-low-noise PGIA

OSC1

GENERATOR

PROGRAMMABLE

two-channel

SINC FIR FILTER

process

CLOCK

for

OSC2

weigh

VD+

CS5531/32/33/34

control,

SRAM/CONTROL

CALIBRATION

INTERFACE

(CS5531/32)

LOGIC

SERIAL

scale

scientific,

DGND

and

SDI

SDO

SCLK

process

and

four-channel

DS289F1

JUL ‘05

medical

control

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