CY7C1041DV3310ZSXI Cypress Semiconductor Corporation., CY7C1041DV3310ZSXI Datasheet

CY7C1041DV3310ZSXI

Manufacturer Part Number

CY7C1041DV3310ZSXI

Description

TSOP44

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1041DV3310ZSXI.pdf (14 pages)

Specifications of CY7C1041DV3310ZSXI

Date_code

09+

Current page: 1 of 14
Download datasheet (383Kb)

Cypress Semiconductor Corporation

Document #: 38-05473 Rev. *D

Features

Note

• Pin- and function-compatible with CY7C1041CV33

• High speed

• Low active power

• Low CMOS standby power

• 2.0 V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• Available in lead-free 48-ball VFBGA, 44-lead (400-mil)

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.

Logic Block Diagram

— t

— I

Molded SOJ and 44-pin TSOP II packages

SB2

=10 ns

= 90 mA @ 10 ns (Industrial)

= 10 mA

•

INPUT BUFFER

DECODER

COLUMN

256K × 16

198 Champion Court

Functional Description

The CY7C1041DV33 is a high-performance CMOS Static

RAM organized as 256K words by 16 bits. Writing to the device

is accomplished by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then

data from I/O pins (I/O

specified on the address pins (A

(BHE) is LOW, then data from I/O pins (I/O

into the location specified on the address pins (A

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O

LOW, then data from memory will appear on I/O

the truth table at the back of this data sheet for a complete

description of Read and Write modes.

The input/output pins (I/O

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

The CY7C1041DV33 is available in a standard 44-pin

400-mil-wide body width SOJ and 44-pin TSOP II package

with center power and ground (revolutionary) pinout, as well

as a 48-ball fine-pitch ball grid array (FBGA) package.

4-Mbit (256K x 16) Static RAM

•

San Jose

I/O

–I/O

CA 95134-1709

BHE

BLE

– I/O

–I/O

[1]

. If Byte HIGH Enable (BHE) is

), is written into the location

–I/O

–A

CY7C1041DV33

) are placed in a

). If Byte HIGH Enable

Revised July 17, 2006

•

–I/O

408-943-2600

to I/O

–A

) is written

. See

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