CY7C1353G100AXC Cypress Semiconductor Corporation., CY7C1353G100AXC Datasheet

CY7C1353G100AXC

Manufacturer Part Number

CY7C1353G100AXC

Description

TQFP-100

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1353G100AXC.pdf (13 pages)

Specifications of CY7C1353G100AXC

Date_code

08+

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Cypress Semiconductor Corporation

Document #: 38-05515 Rev. *E

Features

Note:

CEN

Logic Block Diagram

CLK

1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

• Supports up to 133-MHz bus operations with zero wait

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self timed output buffer control to eliminate the

• Registered inputs for flow-through operation

• Byte Write capability

• 256K x 18 common IO architecture

• 2.5V/3.3V IO power supply (V

• Fast clock-to-output times

• Clock Enable (CEN) pin to suspend operation

• Synchronous self timed writes

• Asynchronous Output Enable

• Available in Pb-free 100-Pin TQFP package

• Burst Capability — linear or interleaved burst order

• Low standby power

states

— Data is transferred on every clock

need to use OE

— 6.5 ns (for 133-MHz device)

A0, A1, A

ADV/LD

MODE

ADDRESS

DDQ

)

READ LOGIC

CONTROL

WRITE ADDRESS

SLEEP

AND DATA COHERENCY

WRITE REGISTRY

CONTROL LOGIC

•

ADV/LD

198 Champion Court

4-Mbit (256K x 18) Flow-through SRAM

BURST

LOGIC

Functional Description

The CY7C1353G is a 3.3V, 256K x 18 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1353G is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two Byte Write Select

(BW

conducted with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

A0'

A1'

[A:B]

DRIVERS

WRITE

•

) and a Write Enable (WE) input. All writes are

San Jose

with NoBL™ Architecture

MEMORY

ARRAY

CA 95134-1709

INPUT

[1]

Revised July 09, 2007

, CE

CY7C1353G

•

, CE

408-943-2600

) and an

DQs

DQP

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