HYB39S128160CT7 Infineon Technologies AG, HYB39S128160CT7 Datasheet

HYB39S128160CT7

Manufacturer Part Number

HYB39S128160CT7

Description

TSOP54

Manufacturer

Infineon Technologies AG

Datasheet

1.HYB39S128160CT7.pdf (48 pages)

Specifications of HYB39S128160CT7

Date_code

04+

Current page: 1 of 48
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128-MBit Synchronous DRAM

• High Performance:

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• 0 to 70 C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2, 3

• Programmable Wrap Sequence: Sequential

• Programmable Burst Length: 1, 2, 4, 8

The HYB 39S128400/800/160CT are four bank Synchronous DRAM’s organized as 4

banks

devices achieve high speed data transfer rates by employing a chip architecture that prefetches

multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using

the Infineon advanced 0.17 micron process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single

3.3 V

INFINEON Technologies

or Interleave

CK3

AC3

CK2

AC2

0.3 V power supply and are available in TSOPII packages.

8MBit x4, 4 banks

-7

143

5.4

7.5

5.4

-7.5

133

7.5

5.4

-8

125

4MBit x8 and 4 banks

Units

MHz

• Multiple Burst Read with Single Write

• Automatic and Controlled Precharge

• Data Mask for Read/Write Control (x4, x8)

• Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Power Down and Clock Suspend Mode

• 4096 Refresh Cycles / 64 ms

• Random Column Address every CLK

• Single 3.3 V

• LVTTL Interface

• Plastic Packages:

• -7

Operation

Command

(1-N Rule)

P-TSOPII-54 400mil x 875 mil width

-7.5 for PC 133 3-3-3 applications

-8

(x4, x8, x16)

2Mbit x16 respectively. These synchronous

128-MBit Synchronous DRAM

HYB 39S128400/800/160CT(L)

for PC 133 2-2-2 applications

for PC100 2-2-2 applications

0.3 V Power Supply

7.01

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