MT46V8M16TG75DTR Micron Semiconductor Products, MT46V8M16TG75DTR Datasheet

MT46V8M16TG75DTR

Manufacturer Part Number

MT46V8M16TG75DTR

Description

TSOP8

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT46V16M8P6TD.pdf (81 pages)

Specifications of MT46V8M16TG75DTR

Date_code

06+

Current page: 1 of 81
Download datasheet (7Mb)

Table 1:

Double Data Rate (DDR) SDRAM

MT46V32M4 – 8 Meg x 4 x 4 Banks

MT46V16M8 – 4 Meg x 8 x 4 Banks

MT46V8M16 – 2 Meg x 16 x 4 Banks

Features

• V

• Bidirectional data strobe (DQS) transmitted/

• Internal, pipelined double-data-rate (DDR)

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

• Programmable burst lengths: 2, 4, or 8

• Auto refresh and self refresh modes

• Longer lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2 compatible)

• Concurrent auto precharge option is supported

•

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

128Mb_DDR_x4x8x16_D1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Speed Grade

received with data, i.e., source-synchronous data

capture (x16 has two – one per byte)

architecture; two data accesses per clock cycle

aligned with data for WRITEs

(x16 has two – one per byte)

RAS lockout supported (

-75E/-75Z

-5B

= +2.5V ±0.2V, V

= +2.6V ±0.1V, V

-6T

-75

Key Timing Parameters

CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and

CL = 3 (-5B)

CL = 2

133

100

Q = +2.5V ±0.2V

Q = +2.6V ±0.1V (DDR400)

RAP =

Clock Rate (MHz)

RCD)

CL = 2.5

167

133

CL = 3

200

n/a

Notes: 1. Not recommended for new designs

Options

• Configuration

• Plastic package – OCPL

• Timing – cycle time

• Self refresh

• Temperature rating

• Revision

– 32 Meg x 4 (8 Meg x 4 x 4 banks)

– 16 Meg x 8 (4 Meg x 8 x 4 banks)

– 8 Meg x 16 (2 Meg x 16 x 4 banks)

– 66-pin TSOP

– 66-pin TSOP (Pb-free)

– 5ns @ CL = 3 (DDR400)

– 6ns @ CL = 2.5 (DDR333)

– 7.5ns @ CL = 2 (DDR266)

– 7.5ns @ CL = 2 (DDR266A)

– 7.5ns @ CL = 2.5 (DDR266B)

– Standard

– Low-power self refresh

– Commercial (0°C to 70°C)

– Industrial (–40°C to +85°C)

(TSOP only)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Data Out

Window

1.6ns

2.0ns

2.5ns

128Mb: x4, x8, x16 DDR SDRAM

Window

±0.70ns

±0.75ns

Access

Marking

DQS–DQ

+0.40ns

+0.45ns

+0.50ns

Features

Skew

32M4

16M8

8M16

None

-75E

-75Z

-5B

-6T

-75

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