CY7C1520AV18-200BZXC Cypress Semiconductor Corporation., CY7C1520AV18-200BZXC Datasheet

CY7C1520AV18-200BZXC

Manufacturer Part Number

CY7C1520AV18-200BZXC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1520AV18-200BZI.pdf (30 pages)

2.CY7C1520AV18-200BZI.pdf (28 pages)

Specifications of CY7C1520AV18-200BZXC

Package

BGA

Date_code

10+

Current page: 1 of 30
Download datasheet (750Kb)

Features

■

Configurations

CY7C1516AV18 – 8M x 8

CY7C1527AV18 – 8M x 9

CY7C1518AV18 – 4M x 18

CY7C1520AV18 – 2M x 36

Selection Guide

Cypress Semiconductor Corporation

Document Number: 001-06982 Rev. *C

Maximum Operating Frequency

Maximum Operating Current

72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

300 MHz clock for high bandwidth

2-word burst for reducing address bus frequency

Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

Two input clocks (K and K) for precise DDR timing

❐

Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

Synchronous internally self-timed writes

DDR-II operates with 1.5 cycle read latency when Delay Lock

Loop (DLL) is enabled

Operates as a DDR-I device with 1 cycle read latency in DLL

off mode

1.8V core power supply with HSTL inputs and outputs

Variable drive HSTL output buffers

Expanded HSTL output voltage (1.4V–V

Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

Delay Lock Loop (DLL) for accurate data placement

SRAM uses rising edges only

Description

x18

x36

•

300 MHz

)

1080

300

900

940

198 Champion Court

278 MHz

278

860

985

Functional Description

The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and

CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1516AV18

and two 9-bit words in the case of CY7C1527AV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1516AV18 and

CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1518AV18 and two 36-bit words in the case of

CY7C1520AV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

72-Mbit DDR-II SRAM 2-Word

•

250 MHz

CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

250

800

900

San Jose

CA 95134-1709

200 MHz

Burst Architecture

200

700

735

Revised September 27, 2007

167 MHz

167

650

•

408-943-2600

MHz

Unit

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