IC LATCH QUAD BISTABLE 16DIP

74HC75N,652

Manufacturer Part Number74HC75N,652
DescriptionIC LATCH QUAD BISTABLE 16DIP
ManufacturerNXP Semiconductors
Series74HC
74HC75N,652 datasheet
 


Specifications of 74HC75N,652

Logic TypeD-Type Transparent LatchPackage / Case16-DIP (0.300", 7.62mm)
Circuit2:2Output TypeDifferential
Voltage - Supply2 V ~ 6 VIndependent Circuits2
Delay Time - Propagation11nsCurrent - Output High, Low5.2mA, 5.2mA
Operating Temperature-40°C ~ 125°CMounting TypeThrough Hole
Number Of Circuits4Logic Family74HC
PolarityInverting/Non-InvertingHigh Level Output Current- 5.2 mA
Low Level Output Current5.2 mAPropagation Delay Time25 ns
Supply Voltage (max)6 VSupply Voltage (min)2 V
Maximum Operating Temperature+ 125 CMinimum Operating Temperature- 40 C
Mounting StyleThrough HoleLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names568-1493-5
74HC75N
933669870652
  
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74HC75
Quad bistable transparant latch
Rev. 03 — 12 November 2004
1. General description
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC
standard no. 7A.
The 74HC75 has four bistable latches. The two latches are simultaneously controlled by
one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data
enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs
(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time
prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched
outputs remain stable as long as the LEnn is LOW.
2. Features
Complementary Q and Q outputs
V
CC
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 C to +80 C and from 40 C to +125 C.
and GND on the center pins
Product data sheet

74HC75N,652 Summary of contents

  • Page 1

    Quad bistable transparant latch Rev. 03 — 12 November 2004 1. General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC ...

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    Philips Semiconductors 3. Quick reference data Table 1: Symbol PHL PLH [ input frequency in MHz output frequency in MHz ...

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    Philips Semiconductors 5. Functional diagram Fig 1. Functional diagram 9397 750 13816 Product data sheet LE12 ...

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    Philips Semiconductors Fig 3. IEC logic symbol 6. Pinning information 6.1 Pinning Fig 5. Pin configuration 9397 750 13816 Product data sheet ...

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    Philips Semiconductors 6.2 Pin description Table 3: Symbol LE34 GND LE12 Functional description 7.1 Function table Table 4: Operating mode Data enabled Data latched [1] ...

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    Philips Semiconductors 8. Limiting values Table 5: In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol GND ...

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    Philips Semiconductors 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level input voltage IH V LOW-level input voltage IL V ...

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    Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current LI I quiescent supply current ...

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    Philips Semiconductors 11. Dynamic characteristics Table 8: Dynamic characteristics GND = ns pF; unless otherwise specified, see Symbol Parameter amb ...

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    Philips Semiconductors Table 8: Dynamic characteristics GND = ns pF; unless otherwise specified, see Symbol Parameter C power dissipation PD capacitance per latch ...

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    Philips Semiconductors Table 8: Dynamic characteristics GND = ns pF; unless otherwise specified, see Symbol Parameter +125 C amb ...

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    Philips Semiconductors 12. Waveforms Fig 6. Waveforms showing the data input (nD) to output (nQ) propagation delays and the Fig 7. Waveforms showing the data input (nD) to output (nQ) propagation delays and the Fig 8. Waveforms showing the data ...

  • Page 13

    Philips Semiconductors Fig 9. Waveforms showing the latch enable input (LEnn) pulse width, the latch enable Fig 10. Load circuitry for switching times Table 9: Supply V CC 2.0 V 4.5 V 6.0 V 5.0 V 9397 750 13816 Product ...

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    Philips Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. ...

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    Philips Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 ...

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    Philips Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1.80 mm ...

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    Philips Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

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    Philips Semiconductors 14. Revision history Table 10: Revision history Document ID Release date Data sheet status 74HC75_3 20041112 • Modifications: The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips ...

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    Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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    Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...