CY7C128A-20DMB Cypress Semiconductor Corporation., CY7C128A-20DMB Datasheet

CY7C128A-20DMB

Manufacturer Part Number

CY7C128A-20DMB

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C128A-20DMB.pdf (9 pages)

Specifications of CY7C128A-20DMB

Date_code

00+

Available stocks

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Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C128A-20DMB

Manufacturer:

Quantity:

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C128A-20DMB

Manufacturer:

Quantity:

650

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C128A-20DMB

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Features

Selection Guide

Cypress Semiconductor Corporation

• Automatic power-down when deselected

• CMOS for optimum speed/power

• High speed

• Low active power

• Low standby power

• TTL-compatible inputs and outputs

• Capable of withstanding greater than 2001V electro-

• V

Maximum Access Time (ns)

Maximum Operating

Current (mA)

Maximum Standby

Current (mA)

static discharge

— 15 ns

— 440 mW (commercial)

— 550 mW (military)

— 110 mW

Logic Block Diagram

of 2.2V

INPUT BUFFER

128 x 16 x 8

DECODER

COLUMN

ARRAY

Commercial

Military

Commercial

Military

POWER

DOWN

•

3901 North First Street

7C128A–15

40/40

120

Functional Description

The CY7C128A is a high-performance CMOS static RAM or-

ganized as 2048 words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE), and active LOW

output enable (OE) and three-state drivers. The CY7C128A

has an automatic power-down feature, reducing the power

consumption by 83% when deselected.

Writing to the device is accomplished when the chip enable

(CE) and write enable (WE) inputs are both LOW.

Data on the eight I/O pins (I/O

memory location specified on the address pins (A

Reading the device is accomplished by taking chip enable

(CE) and output enable (OE) LOW while write enable (WE) remains

HIGH. Under these conditions, the contents of the memory location

specified on the address pins will appear on the eight I/O pins.

The I/O pins remain in high-impedance state when chip enable

(CE) or output enable (OE) is HIGH or write enable (WE) is LOW.

The CY7C128A utilizes a die coat to insure alpha immunity.

7C128A–20

C128A–1

40/20

100

125

I/O

•

San Jose

Pin Configurations

7C128A–25

December 1988 – Revised December 1992

100

125

•

2K x 8 Static RAM

I/O

GND

I/O

CA 95134

through I/O

7C128A–35

DIP/SOJ

Top View

11 12 13 14 15

Top View

3 2 1

7C128A

LCC

100

CY7C128A

•

) is written into the

I/O

C128A–2

408-943-2600

C128A–3

7C128A–45

100

through

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