CS5378-ISZ Cirrus Logic, Inc., CS5378-ISZ Datasheet

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CS5378-ISZ

Manufacturer Part Number
CS5378-ISZ
Description
Manufacturer
Cirrus Logic, Inc.
Datasheets

Specifications of CS5378-ISZ

Pack_quantity
47
Comm_code
85423990
Lead_time
119

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Features
http://www.cirrus.com
Single-channel Digital Decimation Filter
Integrated PLL for Clock Generation
Selectable Output Word Rate
Digital Gain and Offset Corrections
Test DAC Bit-stream Generator
Time Break Controller, General-purpose I/O
Microcontroller or EEPROM Configuration
Small-footprint, 28-pin SSOP Package
Low Power Consumption
Flexible Power Supplies
Multiple On-chip FIR and IIR Coefficient Sets
Programmable Coefficients for Custom Filters
Synchronous Operation
1.024 MHz, 2.048 MHz, or 4.096 MHz Input
Standard Clock or Manchester Input
4000, 2000, 1000, 500, 333, 250 SPS
200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS
Sine Wave or Impulse Output Mode
16 mW at 500 SPS OWR
I/O Interface and PLL: 3.3 V or 5.0 V
Digital Logic Core: 2.5 V, 3.3 V or 5.0 V
I
Low-power Single-channel Decimation Filter
Modulator Data Interface
Decimation and
Filtering Engine
Serial Interface
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
Description
The CS5378 is a multi-function digital filter utilizing a low-
power signal processing architecture to achieve efficient
filtering for a delta-sigma-type modulator. By combining
the CS5378 with a CS3301/02 differential amplifier, a
CS5371 modulator, and a CS4373 test DAC, a synchro-
nous high-resolution measurement system can be
designed quickly and easily.
Digital filter coefficients for the CS5378 FIR and IIR filters
are included on-chip for a simple setup, or they can be
programmed for custom applications. Selectable digital
filter decimation ratios produce output word rates from
4000 SPS to 1 SPS, resulting in measurement band-
widths ranging from 1600 Hz down to 400 mHz when
using the on-chip coefficient sets.
The CS5378 includes integrated peripherals to simplify
system design: a low-jitter PLL for standard clock or
manchester inputs, offset and gain corrections, a test
DAC bit stream generator, a time break controller, and
eight general-purpose I/O pins.
ORDERING INFORMATION
Reset, Synchronization
PLL, Clock Generation
Time Break Controller
General Purpose I/O
See
Test Bit Stream
Controller
GPIO
page
86.
CLK
MCLK
RESET
SYNC
MSYNC
TIMEB
TBSDATA
GPIO7:BOOT
GPIO6:PLL2
GPIO5:PLL1
GPIO4:PLL0
GPIO3
GPIO2
GPIO1
GPIO0
CS5378
DS639F1
OCT ‘05

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