MT48LC16M16A2P-7EIT:D Micron Semiconductor Products, MT48LC16M16A2P-7EIT:D Datasheet

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MT48LC16M16A2P-7EIT:D

Manufacturer Part Number
MT48LC16M16A2P-7EIT:D
Description
Manufacturer
Micron Semiconductor Products
Datasheet

Specifications of MT48LC16M16A2P-7EIT:D

Pack_quantity
108
Comm_code
85423231
Lead_time
56
Eccn
EAR99

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Quantity:
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Synchronous DRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site:
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Table 1:
Table 2:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_1.fm - Rev. L 10/07 EN
Parameter
Configuration
Refresh count
Row
addressing
Bank
addressing
Column
addressing
Speed
Grade
edge of system clock
changed every clock cycle
and auto refresh modes
-6A
-7E
-75
-7E
-75
Frequency
MT48LC16M16A2TG-75:D
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
Clock
Address Table
Key Timing Parameters
CL = CAS (READ) latency
Products and specifications discussed herein are subject to change by Micron without notice.
8K (A0–A12) 8K (A0–A12) 8K (A0–A12)
4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
64 Meg x 4 32 Meg x 8 16 Meg x 16
Part Number Example:
16 Meg x 4
2K (A0–A9,
x 4 banks
A11)
8K
CL = 2
5.4ns
Access Time
6ns
1K (A0–A9)
8 Meg x 8
x 4 banks
CL = 3
5.4ns
5.4ns
5.4ns
8K
Setup
Time
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
512 (A0–A8)
4 Meg x 16
x 4 banks
8K
Time
Hold
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
www.micron.com
1
Notes: 1. Refer to Micron technical note: TN-48-05.
Options
• Configurations
• Write recovery (
• Plastic package – OCPL
• Timing (cycle time)
• Self refresh
• Operating temperature range
• Design revision
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
– 54-pin TSOP II OCPL
– 54-pin TSOP II OCPL
– 60-ball FBGA (x4, x8) (8mm x 16mm)
– 60-ball FBGA (x4, x8) Pb-free
– 54-ball VFBGA (x16) (8mm x 14 mm)
– 54-ball VFBGA (x16) Pb-free
– 6.0ns @ CL = 3 (x8, x16 only)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– Standard
– Low power
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
t
(standard)
Pb-free
(8mm x 16mm)
(8mm x 14 mm)
WR = “2 CLK”
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2. Off-center parting line.
3. Contact Micron for availability.
t
WR)
1
256Mb: x4, x8, x16 SDRAM
2
2
2
(400 mil)
(400 mil)
©1999 Micron Technology, Inc. All rights reserved.
Marking
Features
16M16
64M4
None
None
32M8
-6A
-7E
BG
-75
TG
BB
FG
A2
FB
:D
L
IT
P
3

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