MT48LC4M16A2P-7E:J Micron Semiconductor Products, MT48LC4M16A2P-7E:J Datasheet - Page 4

• Manufacturer Part Number: MT48LC4M16A2P-7E:J
• Description: 4MX16 SDRAM PLASTIC COMMERCIAL PBF TSOP 3.3V
• Manufacturer: Micron Semiconductor Products

Specifications of MT48LC4M16A2P-7E:J

• Pack_quantity: 100
• Comm_code: 85423231
• Lead_time: 84
• Eccn: EAR99

64Mb: x4, x8, x16 SDRAM
Features
List of Figures
Figure 1: 16 Meg x 4 Functional Block Diagram ................................................................................................. 8
Figure 2: 8 Meg x 8 Functional Block Diagram ................................................................................................... 9
Figure 3: 4 Meg x 16 Functional Block Diagram ............................................................................................... 10
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11
Figure 5: 54-Ball VFBGA x16 (Top View) ......................................................................................................... 12
Figure 6: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 14
Figure 7: 54-Ball VFBGA (8mm x 8mm) – Package Codes F4/B4 ....................................................................... 15
Figure 8: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 17
Figure 9: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) .............................................. 18
Figure 10: ACTIVE Command ........................................................................................................................ 29
Figure 11: READ Command ........................................................................................................................... 30
Figure 12: WRITE Command ......................................................................................................................... 31
Figure 13: PRECHARGE Command ................................................................................................................ 32
Figure 14: Initialize and Load Mode Register .................................................................................................. 40
Figure 15: Mode Register Definition ............................................................................................................... 42
Figure 16: CAS Latency .................................................................................................................................. 45
t
t
t
Figure 17: Example: Meeting
RCD (MIN) When 2 <
RCD (MIN)/
CK < 3 .......................................................... 46
Figure 18: Consecutive READ Bursts .............................................................................................................. 48
Figure 19: Random READ Accesses ................................................................................................................ 49
Figure 20: READ-to-WRITE ............................................................................................................................ 50
Figure 21: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51
Figure 22: READ-to-PRECHARGE .................................................................................................................. 51
Figure 23: Terminating a READ Burst ............................................................................................................. 52
Figure 24: Alternating Bank Read Accesses ..................................................................................................... 53
Figure 25: READ Continuous Page Burst ......................................................................................................... 54
Figure 26: READ – DQM Operation ................................................................................................................ 55
Figure 27: WRITE Burst ................................................................................................................................. 56
Figure 28: WRITE-to-WRITE .......................................................................................................................... 57
Figure 29: Random WRITE Cycles .................................................................................................................. 58
Figure 30: WRITE-to-READ ............................................................................................................................ 58
Figure 31: WRITE-to-PRECHARGE ................................................................................................................. 59
Figure 32: Terminating a WRITE Burst ............................................................................................................ 60
Figure 33: Alternating Bank Write Accesses ..................................................................................................... 61
Figure 34: WRITE – Continuous Page Burst ..................................................................................................... 62
Figure 35: WRITE – DQM Operation ............................................................................................................... 63
Figure 36: READ With Auto Precharge Interrupted by a READ ......................................................................... 65
Figure 37: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 66
Figure 38: READ With Auto Precharge ............................................................................................................ 67
Figure 39: READ Without Auto Precharge ....................................................................................................... 68
Figure 40: Single READ With Auto Precharge .................................................................................................. 69
Figure 41: Single READ Without Auto Precharge ............................................................................................. 70
Figure 42: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 71
Figure 43: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71
Figure 44: WRITE With Auto Precharge ........................................................................................................... 72
Figure 45: WRITE Without Auto Precharge ..................................................................................................... 73
Figure 46: Single WRITE With Auto Precharge ................................................................................................. 74
Figure 47: Single WRITE Without Auto Precharge ............................................................................................ 75
Figure 48: Auto Refresh Mode ........................................................................................................................ 77
Figure 49: Self Refresh Mode .......................................................................................................................... 79
Figure 50: Power-Down Mode ........................................................................................................................ 80
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64Mb_sdr.pdf - Rev. Q 2/12 EN
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