ZL50060 ZARLINK [Zarlink Semiconductor Inc], ZL50060 Datasheet
ZL50060
Related parts for ZL50060
ZL50060 Summary of contents
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... Timing Unit C8i PLL V DD_PLL Figure 1 - ZL50060/1 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. 16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion ( ...
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... Note 1: For software compatibility between ZL50061 and MT90869, please refer to Section 2.6. Applications • Central Office Switches (Class 5) • Media Gateways • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers ZL50060 Zarlink Semiconductor Inc. Data Sheet ...
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... Device Overview The ZL50060 and ZL50061 are two different packages of the same device. The ZL50060/1 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports have two independent modes of operation, either 32 input and 32 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any combination input and 16 output streams operated at 32 ...
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... Local Connection Memory 9.2 Backplane Connection Memory 9.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.1 Memory Block Programming Procedure 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 Test Access Port (TAP 11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ZL50060/1 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Bit Rate Registers (LOBRR0 - LOBRR31 14.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.13.1 Backplane Input Bit Rate Registers (BIBRR0 - BIBRR31 14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR31 14.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.15 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 15.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 16.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ZL50060/1 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50060/1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50061 PBGA Connections (272 PBGA mm) Pin Diagram (as viewed through top of package Figure 3 - ZL50060 PBGA Connections (256 PBGA mm) Pin Diagram (as viewed through top of package Figure 4 - 16,384 x 16,384 Channels (16 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5 - 8,192 x 8,192 Channels (16 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration ...
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... Table 44 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 45 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 46 - Local Input Bit Rate Register (LIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 47 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 48 - Local Output Bit Rate Register (LOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ZL50060/1 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 54 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 55 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ZL50060/1 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... NC NC BSTi29 VDD_ D13 CORE CORE W BSTi23 BSTi24 BSTi25 BSTi30 D15 D12 Y BSTi26 BSTi27 NC BSTi31 D14 D11 Figure 2 - ZL50061 PBGA Connections (272 PBGA mm) Pin Diagram ZL50060 VDD_ A8 A11 A14 DS ODE DTA TCK CORE A5 A7 A10 NC ...
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... BSTi13 BSTi14 BSTi15 P BSTi17 BSTi18 BSTi19 BSTi20 R BSTi22 BSTi23 BSTi24 BSTi25 T BSTi27 BSTi28 BSTi29 BSTi30 Figure 3 - ZL50060 PBGA Connections (256 PBGA mm) Pin Diagram ZL50060 R/W CS BCSTo0 BCSTo1 BCSTo2 BCSTo3 LCSTo3 LCSTo2 LCSTo1 LCSTo0 ...
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... U14 C8o V13 FP8o V14 C16o W13 ZL50060/1 ZL50060 Package (256-ball PBGA) T10 Master Clock (5 V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the ...
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... U1, W1, W2, R1, R2, R3, W3, Y1, Y2, R4, R5, T1, U5, V4, W4, T2, T3, T4 ZL50060/1 ZL50060 Package (256-ball PBGA) P11 Frame Pulse Output (5 V Tolerant Three-state Output). When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 61 ns-wide frame pulse ...
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... Y20, Y17, T13, T14, Y18, Y19 Backplane and Local Outputs and Control ODE A12 ZL50060/1 ZL50060 Package (256-ball PBGA) Local Serial Input Streams Tolerant Inputs with Internal Pull-downs). L13, L14, In Local Non-32 Mbps Mode, these pins accept serial TDM ...
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... B1, B2, B3, C3, C4, D1, C1, C2, D1, D2, D3, D4, D2, D3, E1, E1, E2, E3, E2 ZL50060/1 ZL50060 Package (256-ball PBGA) D5 Backplane Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the BSTo0-31 outputs driven high, and the BCSTo0-3 outputs driven low ...
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... J1, J2, J3, J4 J1, J2, J3, J4 BCSTo0-3 C14, A15, A9, A10, A11, B15, C15 ZL50060/1 ZL50060 Package (256-ball PBGA) Backplane Serial Output Streams Tolerant, Three-state Outputs with Slew-Rate Control). In Backplane Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16 ...
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... C20, D18, D13, D14, D19, D20, D15, D16, E17, E18, E13, E14, E19, E20 ZL50060/1 ZL50060 Package (256-ball PBGA) D12 Local Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the LSTo0-31 outputs driven high, and the LCSTo0-3 outputs driven low ...
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... J20, K17, K18 J13, J14, J15, LCSTo0-3 C17, C16, A16, A15, B16, A16 ZL50060/1 ZL50060 Package (256-ball PBGA) Local Serial Output Streams Tolerant Three-state Outputs with Slew-Rate Control). In Local Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16 ...
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... B11 DS A11 R/W C11 DTA A13 ZL50060/1 ZL50060 Package (256-ball PBGA) Address Tolerant Inputs). These pins form the 15-bit address bus to the internal memories and registers LSB Data Bus Tolerant Inputs/Outputs with Slew-Rate Control). These pins form the 16-bit data bus of the microprocessor port ...
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... E10, F6, F11, N3, P18, T17, J5, J12, K5, U16, V1, V5, K12, L6, L7, Y7, Y11, Y14 ZL50060/1 ZL50060 Package (256-ball PBGA) B11 Device Reset (5 V Tolerant Input with Internal Pull-up). This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, ...
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... IC_OPEN Y12, Y13 IC_GND A2, B17, C3, D6, D7, D8, D16, V11, D9, T6, T7, W10, W11, Y10 ZL50060/1 ZL50060 Package (256-ball PBGA) M10 Power Supply for Analog PLL: +1.8 V Ground. M11 No Connects. These pins are not used and can be tied HIGH, LOW, or left unconnected. N10, N11 Internal Connections - OPEN ...
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... This gives the maximum 16,384 x 16,384 channel capacity. Often a system design needs to differentiate between a Backplane and a Local side needs to put the switch in a bi-directional configuration. In this case, the ZL50060/1 can be used as shown in Figure 5 to give 8,192 x 8,192 channel bi-directional capacity. BSTi0-31 ...
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... Mbps and 16.384 Mbps without loss to the switching capacity. 1.1 Flexible Configuration The ZL50060/1 can be configured non-blocking unidirectional digital switch non-blocking bi-directional digital switch blocking switch with various switching capacities. 1.1.1 ...
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... If the Backplane 32 Mbps Mode is selected by setting the Control Register bit MODE32B HIGH, the settings in BIBRRn and BOBRRn are ignored. Similarly, if the Local 32 Mbps Mode is selected by setting the Control Register bit MODE32L HIGH, the settings in LIBRRn and LOBRRn are ignored. ZL50060/1 23 Zarlink Semiconductor Inc. ...
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... Mbps. When the MODE32L bit in the Control Register is set high, the first 16 input streams, LSTi0-15, operate at 32.768 Mbps and the remaining 16 streams, LSTi16-31, will not be used and must be connected to a defined logic level. ZL50060/1 Rate Selection Capability (for each individual stream) 2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode. ...
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... Backplane Output Bit Rate Register (BOBRR0-31). The Backplane streams can also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 16 output streams, BSTo0-15, operate at 32.768 Mbps and the remaining 16 streams, BSTo16-31, will not be used and must be connected to a defined logic level. ZL50060/1 25 Zarlink Semiconductor Inc. Data Sheet ...
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... The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7, ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50060/1 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse ...
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... GCI-Bus BSTi/LSTi0- (4Mbps) ST-BUS BSTi/LSTi0- (4Mbps) GCI-Bus BSTi/LSTi0-31 0 (2Mbps) ST-BUS BSTi/LSTi0-31 7 (2Mbps) GCI-Bus Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates ZL50060/1 Channel 510 Channel Channel 1 Channel 510 ...
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... Input Frame Pulse and Generated Frame Pulse Alignment The ZL50060/1 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2 ...
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... MHz frequency. Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50060/1, the input clock is 8.192 MHz, and the jitter associated with this clock can have the highest frequency component at 4.096 MHz. ...
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... Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a resolution of 1 bit. Refer to Figure 10 and Figure 11 for Input Bit Delay Timing at 16 Mbps and 8 Mbps data rates, respectively. Refer to Figure 11 for Input Sampling Point Selection Timing at 8 Mbps data rates. ZL50060 ...
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... Bit Delay = 1 Ch254 BSTi/LSTi0-31 Bit Delay = 7 1 Ch254 BSTi/LSTi0-31 2 Bit Delay = 7 3/4 Please refer to Control Register (Section 14.1) for SMPL_MODE definition. Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps ZL50060/1 Ch0 Bit Delay, 1/4 Ch0 ...
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... MHz). For 2 Mbps, 4 Mbps, 8 Mbps or 16 Mbps streams, the advancement can cycles, -4 cycles or -6 cycles, which converts to approximately 0 ns, -15 ns shown in Figure 12. For 32 Mbps streams, the advancement can cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7.6 ns, - -23 ns. ZL50060/1 Ch127 Ch0 0 ...
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... Register bit Table 2 - Local and Backplane Output Enable Control Priority ZL50060/1 Bit Advancement, 0 Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -4 Bit 0 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 Bit 6 LE/BE OSB ...
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... Channel 0 will be transmitted during the C16o clock period numbers 2040, 2048, 8, 16, 24, 32, 40 and 48. 4. With stream L/BSTo8 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1 will be transmitted during the C16o clock period numbers 9 and 17. ZL50060/1 LE/BE OSB ...
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... Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode) ZL50060/1 L/BCSTo2 L/BCSTo3 16 Mbps 8 Mbps 4 Mbps 2 Mbps ...
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... Clock period count is referenced to frame boundary. Note 2: The channel numbers presented relate to the data rate selected for a specific stream. Note 3: 3-1 to 3-4: See above for examples of channel control bits for streams of different data rates. ZL50060/1 L/BCSTo2 L/BCSTo3 16 Mbps 8 Mbps 4 Mbps 2 Mbps 18 19 ...
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... Chan 63 L/BSTo6 Bit 0 Chan 0 Bit 7 (4Mbps) Chan 31 L/BSTo7 Bit 0 Channel 0 Bit 7 (2Mbps) L/BCSTo0 L/BCSTo1 L/BCSTo2 L/BCSTo3 Figure 13 - Local/Backplane Port External High Impedance Control Timing (Non-32 Mbps Mode) ZL50060/1 Channel 255 Chan 0 Chan 0 Chan 127 Chan 127 Bit 5 Bit 4 ...
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... For stream L/BSTo4, the value of the channel control bit for Channel 511 will be transmitted during the C16o clock period number 2036 on L/BCSTo0. 4. For stream L/BSTo5, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock period number 12 on L/BCSTo1. ZL50060/1 38 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) ZL50060/1 Channel No. L/BCSTo2 L/BCSTo3 32 Mbps 3-2 3 ...
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... Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) Note 1: Clock period count is referenced to frame boundary. Note 2: The channel numbers presented relate to the specific stream operating at a data rate of 32.768 Mbps. Note 3: 3-1 to 3-4: See above for examples of channel control bits. ZL50060/1 Allocated Stream No. L/BCSTo1 L/BCSTo2 L/BCSTo3 1 2 ...
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... See “Local Connection Memory Bit Definition,” on page 52 and “Backplane Connection Memory Bit Definition,” on page 53 for programming details. When the LORS/BORS signal is asserted HIGH, the L/BCSTo0-3 outputs directly the values given in LE/BE. ZL50060/1 Channel 1 Channel 510 ...
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... Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps Table 5 - Variable Range for Input Streams Table 6 - Variable Range for Output Streams Input Channel Delay OFF frames + ( ZL50060/1 Input Channel Possible Input channel delay ( ) Number ( 127 0 to 255 0 to 511 ...
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... Serial Input Data Frame N Data (No Delay) Serial Output Data Frame N-2 Data (No Delay) Figure 17 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to ZL50060/1 is set to zero, the data throughput delay (T) is frames + (n - m). Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data ...
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... Frame N Serial Input Data Frame N-1 Data ( > 0) Serial Output Data Frame N-3 Data Figure 20 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to ZL50060/1 Frame N+1 Frame N+2 Frame N+3 Input Channel Delay (from 1 to max # of channels) Frame N Data Frame N+1 Data Frame N+2 Data ...
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... The registers listed completely define the transmit and receive stream and channels. When BER transmission is enabled for these channels, the source bits and the Message Mode bits, LSRC and LMM in the Local Connection Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The per-channel enable bits (LE ZL50060 ...
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... Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A delay of an additional 250 s must also be applied before the first microprocessor access is performed following the de-assertion of the RESET pin; this delay is required for determination of the input frame pulse format. ZL50060/1 supply (nominally +3 established before the DD_IO supplies (nominally +1.8 V). The V DD_PLL supply by more than 0 ...
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... Table 8. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated. ZL50060/1 RESET de-assertion Figure 22 - Hardware RESET de-assertion 47 Zarlink Semiconductor Inc ...
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... LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table LBPD2 LBPD1 LBPD0 Table 9 - Local Connection Memory in Block Programming Mode ZL50060/1 Source Stream No. Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] ...
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... Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register. 11.0 JTAG Port The ZL50060/1 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. 11.1 Test Access Port (TAP) The Test Access Port (TAP) consists of four input pins and one output pin described as follows: • ...
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... TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when not driven from an external source. This pin MUST be pulled low for normal operation. 11.2 TAP Registers The ZL50060/1 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an Instruction Register and three Test Data Registers. 11.2.1 Test Instruction Register The JTAG interface contains a four-bit instruction register ...
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... Diagram for Different Data Rates for the arrival order of the bits. Table 12 - Local Data Memory (LDM) Bits Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. ZL50060/1 Description Description 51 Zarlink Semiconductor Inc ...
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... When HIGH, the channel is active. 12:8 LSAB[4:0] Source Stream Address Bits The binary value of these 5 bits represents the input stream number. Ignored when LMM is set HIGH. Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching ZL50060/1 Description Description 52 Zarlink Semiconductor Inc. Data Sheet . ...
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... The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-31) in place of data defined by the Source Control, Stream and Channel Address bits. ZL50060/1 Description Description 53 Zarlink Semiconductor Inc ...
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... When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the BORS pin. When HIGH, the channel is active. 12:9 BSAB[3:0] Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when BMM is set HIGH. ZL50060/1 Description Description 54 Zarlink Semiconductor Inc. Data Sheet . ...
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... Local Input Bit Rate Register 0 - 31, LIBRR0 - 00ED - 010C Local Output Bit Rate Register 0 - 31, LOBRR0 - 010D - 012C Backplane Input Bit Rate Register 0 - 31, BIBRR0 - Table 18 - Address Map for Registers (A14 = 0) ZL50060/1 Description Register 55 Zarlink Semiconductor Inc. Data Sheet ...
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... When LOW, Local streams LSTi0-31 and LSTo0-31 can be individually programmed for data rates Mbps. When HIGH, Local streams LSTi0-15 and LSTo0-15 operate at 32.768 Mbps only and LSTi16-31 and LSTo16-31 are unused. ZL50060/1 Register Description , the Frame Boundary Discriminator can handle both low ...
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... Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 19 - Control Register Bits (continued) ZL50060/1 Description ODE Pin OSB bit BSTo0-31, LSTo0-31 ...
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... ZL50060/1 (a) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (c) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL ...
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... ZL50060/1 (e) Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (f) Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (g) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244ns, ...
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... BPE 0 Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 20 - Block Programming Register Bits ZL50060/1 Description 60 Zarlink Semiconductor Inc. Data Sheet . ...
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... Clear Bit Error Rate Register for Local A LOW to HIGH transition resets the Local internal bit error counter and the Local Bit Error Register (LBERR) to zero. Table 21 - Bit Error Rate Test Control Register (BERCR) Bits ZL50060/1 Description selected for the Backplane ...
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... LCDRn Bit (where for Local Non-32Mbps Mode for Local 32Mbps Mode) 15:9 Reserved 8:0 LCD[8:0] Table 22 - Local Input Channel Delay Register (LCDRn) Bits ZL50060/1 Description Reset Name Value 0 Reserved Must be set to 0 for normal operation 0 Local Channel Delay Register The binary value of these bits refers to the channel delay value for the Local input stream ...
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... Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... 509 Channels 510 Channels 511 Channels Table 23 - Local Input Channel Delay (LCD) Programming Table ZL50060/1 Corresponding Delay Bits LCD8-LCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... 1 1111 1101 1 1111 1110 ...
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... Table 25 illustrates the bit delay and sampling point selection. LIDn LID4 LID3 LID2 Table 25 - Local Input Bit Delay and Sampling Point Programming Table ZL50060 bit. 4 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local Input Bit Delay Register ...
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... Table 25 - Local Input Bit Delay and Sampling Point Programming Table (continued) Zarlink Semiconductor Inc. ZL50060/1 SMPL_MODE SMPL_MODE = LOW Input Data Input Data LID0 Bit Delay Bit Delay ...
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... Channels 3 Channels 4 Channels 5 Channels ... 509 Channels 510 Channels 511 Channels Table 27 - Backplane Input Channel Delay (BCD) Programming Table ZL50060/1 Reset Name Value 0 Reserved Must be set to 0 for normal operation 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream ...
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... The BIDR0 to BIDR31 registers are configured as follows: BIDRn Bit (where for Name Backplane Non-32 Mbps Mode for Backplane 32 Mbps Mode) 15:5 Reserved 4:0 BID[4:0] Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits ZL50060 bit. 4 Reset Description Value 0 Reserved Must be set to 0 for normal operation 0 ...
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... Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table ZL50060 bit periods forward, with resolution bit location -bit increments SMPL_MODE = LOW ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Local Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz 0 (Default) -2 cycles (~15 ns) Table 31 - Local Output Advancement (LOAR) Programming Table ZL50060/1 SMPL_MODE = LOW Input Data BID1 BID0 Bit Delay 0 ...
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... Backplane Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz 0 (Default) -2 cycles (~15 ns) -4 cycles (~31 ns) -6 cycles (~46 ns) Table 33 - Backplane Output Advancement (BOAR) Programming Table ZL50060/1 Local Output Advancement For 32 Mbps Clock Rate 131.072 MHz -2 cycles (~15 ns) -3 cycles (~23 ns) Reset Name ...
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... Value 15:13 Reserved 12:9 LBSSA[3:0] 8:0 LBSCA[8:0] Table 35 - Local BER Start Send Register (LBSSR) Bits in 32 Mbps Mode ZL50060/1 Description 0 Reserved Must be set to 0 for normal operation 0 Local BER Send Stream Address Bits The binary value of these bits refers to the Local output stream which carries the BER data. ...
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... Value 15:9 Reserved 0 8:0 LRXBL[8:0] 0 Table 37 - Local Receive BER Length Register (LRXBLR) Bits ZL50060/1 . The LTXBLR register is configured as follows: B Description Description Reserved Must be set to 0 for normal operation Local Receive BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Receiver ...
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... Bit Name Value 15:0 LBC[15:0] 0 Table 40 - Local BER Count Register (LBCR) Bits ZL50060/1 Description Reserved Must be set to 0 for normal operation Local BER Receive Stream Address Bits The binary value of these bits refers to the Local input stream configured to receive the BER data. ...
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... The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Transmitter. (i.e., Total Channels = BTXBL value + 1) Table 42 - Backplane Transmit BER Length (BTXBLR) Bits ZL50060/1 Description Reserved Must be set to 0 for normal operation Backplane BER Send Stream Address Bits The binary value of these bits refers to the Backplane output stream which carries the BER data ...
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... BER data. 8:0 BBRCA[8:0] 0 Backplane BER Receive Channel Address Bits The binary value of these bits refers to the Backplane input channel at which the BER data starts to be compared. Table 44 - Backplane BER Start Receive Register (BBSRR) Bits ZL50060/1 Description Description 75 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 47 - Local Input Bit Rate (LIBR) Programming Table ZL50060/1 Description Backplane Bit Error Rate Count The binary value of these bits defines the Backplane Bit Error count. If the number of errors exceeds the maximum counter value, this counter will stay at FFFF until the CBERB bit in the BERCR register clears it ...
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... The BIBRR registers are configured as follows: BIBRn Bit Name (for 31) 15:2 Reserved 1:0 BIBR[1:0] Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits ZL50060/1 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local Output Bit Rate LOBR1 LOBR0 Bit rate for stream n ...
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... BOBRn Bit Name (for 31) 15:2 Reserved 1:0 BOBR[1:0] Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits MODE32B Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table ZL50060/1 BIBR1 BIBR0 Bit rate for stream Mbps Mbps Mbps 1 1 ...
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... This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. 2 BISTSCL 0 Local Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Table 54 - Memory BIST Register (MBISTR) Bits ZL50060/1 Description 79 Zarlink Semiconductor Inc. Data Sheet ...
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... The DIR register is configured as follows: Bit Name Reset Value 15:8 Reserved 7:4 RC[3:0] 3 Reserved 2:0 DID[2:0] Table 55 - Device Identification Register (DIR) Bits ZL50060/1 Description 0 Reserved Will read 0 in normal operation 0000 Revision Control Bits 0 Reserved Will read 0 in normal operation 000 Device ID 80 Zarlink Semiconductor Inc ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Operating Temperature 2 Positive Supply 3 Positive Supply 4 Positive Supply 5 Input Voltage 6 Input Voltage Tolerant Inputs Voltages are with respect to ground (V ) unless otherwise stated. SS ZL50060/1 Symbol Min. V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V ...
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... Output Low Voltage High impedance Leakage Output Pin Capacitance S Voltages are with respect to ground (V ) unless otherwise stated. ss Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) ZL50060/1 Sym. Min. Typ. Max DD_Core I 240 290 DD_Core I 100 ...
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... FP8o Output Delay (from output frame boundary to frame pulse edge) 13 C8o Clock Period 14 C8o Clock Pulse Width High 15 C8o Clock Pulse Width Low 16 C8o Clock Rise/Fall Time ZL50060/1 Sym. Level Units V 0. DD_IO V 0. DD_IO V 0 ...
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... FP16o Output Delay (from output frame boundary to frame pulse edge) 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low 23 C16o Clock Rise/Fall Time ZL50060/1 Sym. Min. Typ. t 117 122 OFPW16_122 OFPW16_61 t 58 ...
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... Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 25 - Input and Output Clock Timing Diagram for ST-BUS ZL50060/1 t IFPW244 t ...
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... Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 26 - Input and Output Clock Timing Diagram for GCI-Bus ZL50060/1 t IFPW244 t ...
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... Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point 2 Local/Backplane Serial Input Set-up Time 3 Local/Backplane Serial Input Hold Time 4 Output Frame Boundary Offset 5 Local/Backplane Serial Output Delay ZL50060/1 Sym. Min. Typ. Max IDS32 IDS16 t 87 ...
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... CK_int * L/BSTo0-31 Bit1 Bit0 8.192Mbps Ch127 Ch127 L/BSTo0-31 Bit0 4.096Mbps Ch63 L/BSTo0-31 Bit0 2.048Mbps Ch31 Note *: CK_int is the internal clock signal of 131.072MHz Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) ZL50060/1 t IDS8 t SIS8 t SIH8 IDS4 t SIS4 t SIH4 Bit7 ...
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... Ch255 Ch255 FP8o C8o CK_int * L/BSTo0-15 Bit1 Bit1 32.768Mbps Ch511 Ch511 L/BSTo0-31 Bit0 Ch255 16.384Mbps Note *: CK_int is the internal clock signal of 131.072MHz Figure 28 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) ZL50060/1 t IDS32 t SIS32 t SIH32 IDS16 t SIS16 t SIH16 Bit7 ...
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... CK_int * L/BSTo0-31 Bit6 Bit7 Ch127 Ch127 8.192Mbps Bit7 L/BSTo0-31 Ch63 4.096Mbps L/BSTo0-31 Bit7 2.048Mbps Ch31 Note *: CK_int is the internal clock signal of 131.072MHz Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) ZL50060/1 t IDS8 t SIS8 t SIH8 IDS4 t SIS4 t SIH4 Bit0 ...
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... Ch255 Ch255 FP8o C8o CK_int * L/BSTo0-15 Bit5 Bit6 32.768Mbps Ch511 Ch511 L/BSTo0-31 Bit7 Ch255 16.384Mbps Note *: CK_int is the internal clock signal of 131.072MHz Figure 30 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) ZL50060/1 t IDS32 t SIS32 t SIH32 IDS16 t SIS16 t SIH16 Bit0 ...
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... Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to high impedance Note 1: High Impedance is measured by pulling to the appropriate rail with R CLK STo STo Figure 31 - Serial Output and External Control ODE STo ZL50060/1 Sym. Min. Typ. Max. Units ...
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... MHz 13 2 MHz 14 4 MHz ZL50060/1 16.384 Mbps Data Rate 32.768 Mbps Data Rate Jitter Tolerance Jitter Tolerance 1200 1200 150 110 Zarlink Semiconductor Inc ...
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... Note 2: There must be a minimum between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access). ZL50060/1 Sym. Min. Typ. Max CSS ...
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... DS CS R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 33 - Motorola Non-Multiplexed Bus Timing ZL50060/1 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 95 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH RDH V TT ...
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... TDi Input Hold Time 8 TDo Output Delay 9 TRST pulse width †Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST Figure 34 - JTAG Test Port Timing Diagram ZL50060/1 Sym. Min. Typ. t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes: ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...