ZL50060 ZARLINK [Zarlink Semiconductor Inc], ZL50060 Datasheet - Page 34

• Manufacturer Part Number: ZL50060
• Description: 16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.1
The data (channel control bit) transmitted by L/BCSTo0-3 replicates the Local/Backplane Output Enable (LE/BE)
bit of the Local/Backplane Connection Memory, with a LOW state indicating the channel to be set to high
impedance. Refer to “Local Connection Memory Bit Definition,” on page 52 and “Backplane Connection Memory Bit
Definition,” on page 53 for more details.
The L/BCSTo0-3 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the
per-channel high impedance state for a specific stream. Eight output streams are allocated to each control line as
follows:
•
•
•
•
The channel control bit location, within a frame period, for each channel of the Local/Backplane output streams is
presented in Table 3, L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode).
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
1. The channel control bit corresponding to Stream 0, Channel 0, L/BSTo0_Ch0, is transmitted on L/BCSTo0 and
2. The channel control bit corresponding to Stream 28, Channel 0, L/BSTo28_Ch0, is transmitted on L/BCSTo0 in
The L/BCSTo0-3 pins output data at a constant data rate of 16.384Mbps, independent of the data rate selected for
the individual output streams, L/BSTo0-31. Streams at data rates lower than 16.384 Mbps will have the value of
their respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for
8.192 Mbps streams, four times for 4.096 Mbps streams and eight times for 2.048 Mbps streams. The channel
control bit is not repeated for 16.384 Mbps streams.
Examples are presented, with reference to Table 3:
3. With stream L/BSTo4 selected to operate at a data rate of 2.048Mbps, the value of the channel control bit for
4. With stream L/BSTo8 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1
L/BCSTo0 outputs the channel control bits for streams L/BSTo0, 4, 8, 12, 16, 20, 24, and 28
L/BCSTo1 outputs the channel control bits for streams L/BSTo1, 5, 9, 13, 17, 21, 25, and 29
L/BCSTo2 outputs the channel control bits for streams L/BSTo2, 6, 10, 14, 18, 22, 26 and 30
L/BCSTo3 outputs the channel control bits for streams L/BSTo3, 7, 11, 15, 19, 23, 27 and 31
is advanced, relative to the frame boundary, by 10 periods of C16o.
advance of the frame boundary by three periods of output clock, C16o. Similarly, the channel control bits for
L/BSTo29_Ch0, L/BSTo30_Ch0 and L/BSTo31_Ch0 are advanced relative to the frame boundary by three
periods of C16o, on L/BCSTo1, L/BCSTo2 and L/BCSTo3, respectively.
Channel 0 will be transmitted during the C16o clock period numbers 2040, 2048, 8, 16, 24, 32, 40 and 48.
will be transmitted during the C16o clock period numbers 9 and 17.
(input pin)
LORS/BORS Asserted LOW, Non-32Mbps Mode
RESET
1
1
Table 2 - Local and Backplane Output Enable Control Priority (continued)
(input pin)
ODE
1
1
Register bit)
(Control
OSB
1
1
Zarlink Semiconductor Inc.
Memory bit)
ZL50060/1
Connection
Backplane
(Local /
LE/BE
0
1
34
LORS/BORS
(input pin)
X
1
(HIGH or LOW)
LSTo0-31/
BSTo0-31
ACTIVE
HI-Z
(HIGH or LOW)
LCSTo0-3/
BCSTo0-3
ACTIVE
LOW
Data Sheet