ZL50063GAC ZARLINK [Zarlink Semiconductor Inc], ZL50063GAC Datasheet - Page 28

• Manufacturer Part Number: ZL50063GAC
• Description: 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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10.2
The ZL50063 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
10.2.1
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please
refer to Figure 24 for JTAG test port timing.
10.2.2
10.2.2.1
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50063 core logic.
10.2.2.2
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
10.2.2.3
The JTAG device ID for the ZL50063 is 0C38F14B
Version, Bits <31:28>:0000
Part No., Bits <27:12>:1100 0011 1000 1111
Manufacturer ID, Bits <11:1>:0001 0100 101
Header, Bit <0> (LSB):1
10.3
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 10.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when
not driven from an external source. This pin MUST be pulled low for normal operation.
TAP Registers
Boundary Scan Description Language (BSDL) File
Test Instruction Register
Test Data Registers
The Device Identification Register
The Boundary-Scan Register
The Bypass Register
DD_IO
when not driven from an external source.
Zarlink Semiconductor Inc.
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ZL50063
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Data Sheet