ZL50063GAC ZARLINK [Zarlink Semiconductor Inc], ZL50063GAC Datasheet - Page 32

• Manufacturer Part Number: ZL50063GAC
• Description: 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.0
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
13.0
This section describes the registers that are used in the device.
13.1
Address 0000
The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:
15:13
Bit
12
11
00A3
0023
0063
0083
A14-A0
014D
3FFF
0000
0001
H
H
Control Register (CR)
H
H
MODE[2:0]
Internal Register Mappings
Detailed Register Descriptions
Reserved
- 0032
- 0072
- 0092
- 00B2
SMPL_
MODE
Name
FBD_
H
H
H
H
H
.
H
H
H
H
Reset
Value
Control Register, CR
Block Programming Register, BPR
Local Input Bit Delay Register 0 - 15, LIDR0 - 15
Backplane Input Bit Delay Register 0 - 15, BIDR0 - 15
Local Output Advancement Register 0 - 15, LOAR0 - 15
Backplane Output Advancement Register 0 - 15, BOAR0 - 15
Memory BIST Register, MBISTR
Device Identification Register, DIR
0
0
0
Frame Boundary Discriminator Mode
When set to 111
frequency and high frequency jitter.
When set to 000
frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.
Sample Point Mode
When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR15 and BIDR0 to BIDR15 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR15 and BIDR0 to BIDR15 registers. In
addition the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 13, Table 14, Table 15 and Table 16 for details.
Reserved
Must be set to 0 for normal operation
Table 10 - Address Map for Registers (A14 = 0)
Table 11 - Control Register Bits
B
B
Zarlink Semiconductor Inc.
, the Frame Boundary Discriminator can handle both low
, the Frame Boundary Discriminator is set to handle lower
ZL50063
32
Register
Description
Data Sheet