ZL50234GDC ZARLINK [Zarlink Semiconductor Inc], ZL50234GDC Datasheet
ZL50234GDC
Related parts for ZL50234GDC
ZL50234GDC Summary of contents
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Features • Independent multiple channels of echo cancellation; from 8 channels of 64ms to 4 channels of 128ms with the ability to mix channels at 128ms or 64ms in any combination • Independent Power Down mode for each group of ...
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ZL50234 Description The ZL50234 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The ZL50234 architecture contains 4 groups of two echo cancellers (ECA and ECB) which can be configured to ...
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Data Sheet IC0 V c4i IC0 V IC0 DD1 SS C IC0 IC0 DD1 D NC IC0 V V DD1 IC0 ...
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ZL50234 Pin Description PIN # PIN Name 208-Ball LBGA V A1, A3,A7,A11, A13, SS A15, A16, B2, B6, B8, B12, B14, B15, B16, C3, C5, C7, C9, C11, C12, C13, C14, C16, D4, D8, D10, D12, D13, E3, E4, E14, ...
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Data Sheet Pin Description (continued) PIN # PIN Name 208-Ball LBGA R11 DS R13 CS R5 R/W R7 DTA D0..D7 T2,T4,T6,T8,T9,T11, T13,T15 A0..A10 P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16 ODE B13 Sout A8 Rout B9 Sin B11 Rin B7 B5 F0i A4 C4i ...
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ZL50234 Pin Description (continued) PIN # PIN Name 208-Ball LBGA Fsel H2 PLLVss1 K3 PLLVss2 PLLV K4 DD TMS M2 TDI M1 TDO N1 TCK P1 N2 TRST R3 RESET 1.0 Device Overview The ZL50234 architecture contains 8 echo cancellers ...
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Data Sheet Each echo canceller contains the following main elements (see Figure 4). • Adaptive Filter for estimating the echo channel • Subtractor for cancelling the echo • Double-Talk detector for disabling the filter adaptation during periods of double-talk • ...
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ZL50234 1.2 Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. ...
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Data Sheet by the following equation: where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated ...
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ZL50234 The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will scale the injected noise level down, conversely, raising the value will scale the comfort noise up. Due to differences ...
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Data Sheet 1.6 Instability Detector In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability problems in the adaptive filter. This instability can result in variable pitched ringing or ...
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ZL50234 2.1 Normal Configuration In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously. echo path A Rout PORT2 ...
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Data Sheet Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a transmission device or between two codecs for echo control on analog trunks. 2.3 Extended Delay configuration In this configuration, the two echo ...
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ZL50234 3.2 Bypass The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least ...
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Data Sheet F0i ST-BUS F0i GCI interface Active Channels Rin/Sin Rout/Sout Note: Refer to Figure 12 and Figure 13 for timing details. Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data ...
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ZL50234 6.0 Memory Mapped Control and Status registers Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a “per channel” basis to monitor and ...
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Data Sheet Group 0 Echo Cancellers Registers Group 1 Echo Cancellers Registers Group 2 Echo Cancellers Registers Group 3 Echo Cancellers Registers 6.4 Power Up Sequence On power up, the RESET pin must be held low for 100 s. Forcing ...
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ZL50234 6.5 Power management Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their respective Main Control Register. When a given group is in Power Down mode, the ...
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Data Sheet 7.1 Test Access Port (TAP) The TAP provides access to many test functions of the ZL50234. It consists of four input pins and one output pin. The following pins are found on the TAP. • Test Clock Input ...
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ZL50234 8.0 Register Description Power-up 00 Bit 7 Bit 6 Reset INJDis Reset When high, the power-up initialization is executed. This presets all register bits including this bit and clears the Adaptive Filter coefficients. INJDis When high, the noise injection ...
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Data Sheet Power-up 00 hex Bit 7 Bit 6 TDis PHDis TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled ...
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ZL50234 Power-up 00 hex Bit 7 Bit 6 Reserve TD Reserve Reserved bit. TD Logic high indicates the presence of a 2100Hz tone. DTDet Logic high indicates the presence of a double-talk condition. Reserve Reserved bit. Reserve Reserved bit. Reserve ...
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Data Sheet Amplitude of MU 1.0 Flat Delay (FD ) 7-0 -16 2 Functional Description of Register Bits The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) to ...
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ZL50234 Power-up FB hex Bit 7 Bit 6 NLRun2 InjCtrl NLRun1 NLRun2 When high, the comfort noise level estimator actively rejects double-talk as being background noise. When low, the noise level estimator makes no such distinction. InjCtrl Selects which noise ...
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Data Sheet Power-up 54 hex Bit 7 Bit 6 0 SD2 0 Must be set to zero. SupDec These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast convergence state following a path change, Reset or ...
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ZL50234 Power-up N/A Bit 7 Bit 6 Bit 5 RP15 RP14 RP13 Power-up N/A Bit 7 Bit 6 Bit 5 RP7 RP6 RP5 These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The ...
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Data Sheet Power-up N/A Bit 7 Bit 6 Bit 5 EP15 EP14 EP13 Power-up N/A Bit 7 Bit 6 Bit 5 EP7 EP6 EP5 These peak detector registers allow the user to monitor the error signal peak level. The information ...
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ZL50234 ECA: Non-Linear Processor Threshold Register 2 Power-up 0C ECB: Non-Linear Processor Threshold Register 2 hex Bit 7 Bit 6 Bit 5 NLP15 NLP14 NLP13 ECA: Non-Linear Processor Threshold Register 1 Power-up E0 ECB: Non-Linear Processor Threshold Register 1 hex ...
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Data Sheet Power-up 44 hex Bit 7 Bit 6 Bit 5 0 Rin2 Rin1 Power-up 44 hex Bit 7 Bit 6 Bit 5 0 Sin2 Sin1 This register is used to select gain values on RIN, ROUT, SIN and SOUT. ...
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ZL50234 Power-up 00 Bit 7 Bit 6 WR_all ODE MIRQ Write all control bit: When high, Group 0-3 Echo Cancellers Registers are mapped into 0000 WR_all 0003F which is Group 0 address mapping. Useful to initialize the 4 Groups of ...
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Data Sheet Main Control Register 1 (EC Group 1) Main Control Register 2 (EC Group 2) Main Control Register 3 (EC Group 3) Bit 7 Bit 6 Bit 5 Unused Unused Unused Unused Unused Bits. MTDBI Mask Tone Detector B ...
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ZL50234 Power-up 00 Bit 7 Bit 6 IRQ Unused Unused IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO ...
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Data Sheet Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage (V DD1 2 Core Supply Voltage (V DD2 3 Input Voltage 4 Input Voltage on any 5V Tolerant I/O pins 5 Continuous Current at digital outputs 6 Package power dissipation ...
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ZL50234 AC Electrical Characteristics - Voltages are with respect to ground (V ss Characteristics 1 CMOS Threshold 2 CMOS Rise/Fall Threshold Voltage High 3 CMOS Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated AC ...
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Data Sheet AC Electrical Characteristics Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after ...
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ZL50234 F0i C4i Sout/Rout Sin/Rin MCLK 36 t FPW FPS FPH t SOD Bit 0, Channel 0 Bit 1, Channel SIS SIH Bit 0, Channel 0 Bit 1, Channel 0 Figure 13 - ...
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Data Sheet DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 16 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t ...
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ZL50234 38 Zarlink Semiconductor Inc. Data Sheet ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...