ZL50234GDC ZARLINK [Zarlink Semiconductor Inc], ZL50234GDC Datasheet - Page 8

• Manufacturer Part Number: ZL50234GDC
• Description: 8 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

8
1.2
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the
relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence
speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is
reduced by a factor of 2
adaptation is halted completely.
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The ZL50234 allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
where 0 < DTDT
Example:For DTDT = 0.5625 (-5 dB), the
hexadecimal value becomes
hex(
1.3
Integrated into the ZL50234 is a Path Change Detector. This permits fast reconvergence when a major change
occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence
is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection
of a major path change.
1.4
After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50234
uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as
well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated
ZL50234
0.5625 * 32768
Double-Talk Detector
Path Change Detector
Non-Linear Processor (NLP)
(dec)
)
= 4800
< 1
Slow
hex
relative to normal convergence for non-zero values of Slow. If Slow equals zero,
DTDT
Lsin > Lrin + 20log
(hex)
Zarlink Semiconductor Inc.
= hex(DTDT
10
(dec)
(DTDT)
* 32768)
Data Sheet