ZL50234GDC ZARLINK [Zarlink Semiconductor Inc], ZL50234GDC Datasheet - Page 30

• Manufacturer Part Number: ZL50234GDC
• Description: 8 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

30
ZL50234
WR_all
WR_all
Format
MTDBI
MTDAI
PWUP
MIRQ
ODE
Bit 7
Law
Write all control bit: When high, Group 0-3 Echo Cancellers Registers are mapped into 0000
0003F
as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main Control
Register 0 has the WR_all bit
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE bit
and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or
the ODE input pin is low, the Rout and Sout outputs are high impedance
Control Register 0 has the ODE bit.
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The
Tone Detectors operate as specified in their Echo Canceller B, Control Register 2.
When low, the Tone Detectors Interrupts are active.
Note: Only the Main Control Register 0 has the MIRQ bit.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
A/ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, accept -Law companded
PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo canceller A and B execute their initialization routine which presets their registers, Base
Address+00
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their
specific application.
ODE
Bit 6
Power-up 00
hex
which is Group 0 address mapping. Useful to initialize the 4 Groups of Echo Cancellers
hex
to Base Address+3F
MIRQ
Bit 5
hex
Functional Description of Register Bits
Main Control Register 0 (EC Group 0)
MTDBI
Zarlink Semiconductor Inc.
Bit 4
hex
, to default power up value and clears the Adaptive Filter
MTDAI
Bit 3
R/W Address: 400
Format
Bit 2
.
Note: Only the Main
Bit 1
Law
hex
Data Sheet
PWUP
Bit 0
hex
to