ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 115

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.11.3
CPU Address: hF02
Accessed by CPU (RO)
13.3.11.4
CPU Address:hF03
Accessed by CPU (R/W)
13.3.11.5
CPU Address: hF04
Accessed by CPU (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control
Application Note, ZLAN-37.
Bit [6:0]
Bit [7]
Bit [4:0]:
Bit [7:5]:
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
DPST – Device Port Status Register
DTST – Data read back register
DCR1 - Device Status Register 1
DTST. (Default 00)
Flow control enable
Full duplex port
Fast Ethernet port (if bit [5] not set)
Link is down
Auto negotiation enabled
1: Disable
0: Enable
Gigabit Ethernet port
Reserved
Reserved
Chip initialization completed
Read back index register. This is used for selecting what to read back from
Reserved
Module deleted (for hot swap purpose)
-
-
-
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b00100 - Port 4 Operating mode and Negotiation status
5’b00101 - Port 5 Operating mode and Negotiation status
5’b00110 - Port 6 Operating mode and Negotiation status
5’b00111 - Port 7 Operating mode and Negotiation status
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port GMAC Operating mode and Negotiation status
Zarlink Semiconductor Inc.
ZL50408
115
Data Sheet