ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 31

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.0
4.1
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available, because of advance buffer reservations.
The memory (SRAM) interface is a 64-bit bus, connected to internal memory block. The Receive DMA (RxDMA) is
responsible for multiplexing the data and the address. On a port’s “turn”, the RxDMA will move 8 bytes (or up to the
end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward. But first, the TxQ manager has to decide
whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the
destination. If the frame is not dropped, then the TxQ manager links the frame’s FCB to the correct
per-port-per-class TxQ. The switch response will come with 8 classified results. The TxQ manager will map this
result into the per-port-per-class queue. Unicast TxQ’s are linked lists of transmission jobs, represented by their
associated frames’ FCB’s. There is one linked list for each transmission class for each port. There are 2
transmission classes for each of the 8 RMAC ports, and 4 classes for the GMAC and CPU ports – a total of 24
unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a
port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among
the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling
algorithm.
The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port’s turn, the
TxDMA will move 8 bytes (or up to the EOF) from memory into the port’s associated TxFIFO. After reading the EOF,
the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release
requests.
The frame is transmitted from the TxFIFO to the line.
4.2
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop
can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of
the multicast packet’s destinations. If so, then the frame is dropped at some destinations but not others, and the
FCB is not released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast
queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames).
There are 2 multicast queues for each of the 8 RMAC ports. There are 4 multicast queues for the GMAC and CPU
ports. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for
the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the GMAC
and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping
can be modified through memory configuration command. The multicast queue that is in FIFO format shares the
space in the internal memory block. The size and starting address can also be programmed through memory
configuration command.
Unicast Data Frame Forwarding
Multicast Data Frame Forwarding
Data Forwarding Protocol
Zarlink Semiconductor Inc.
ZL50408
31
Data Sheet