ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 96

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.7
13.3.7.1
I²C Address 0BC, CPU Address:h600
Accessed by CPU and I²C (R/W)
13.3.7.2
I²C Address 0BD, CPU Address:h601
Accessed by CPU and I²C (R/W)
13.3.7.3
I²C Address 0BE, CPU Address:h602)
Accessed by CPU and I²C (R/W)
(Group 6 Address) MISC Group
Bit [4:0]:
Bit [6:5]
Bits [7]:
Bits[3:0]:
Bits[7:4]:
Bits [0]:
Bits[1]:
Bit [2]:
Bit [3]:
MII_OP0 – MII Register Option 0
MII_OP1 – MII Register Option 1
FEN – Feature Register
Vendor specified link status register address (null value means don’t use it)
(Default 00). This is used if the Linkup bit position in the PHY is non-standard
Reserved
Half duplex flow control feature
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
Statistic Counter
0 – Disable (Default)
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
Reserved. Must be 0.
Support DS EF Code.
0 – Disable (Default)
1 – Enable (all ports)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Enable VLAN ID hashing
0 – Disable (Default)
1 – Enable
Zarlink Semiconductor Inc.
ZL50408
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Data Sheet