ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 101

• Manufacturer Part Number: ZL50418GKC
• Description: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY.
14.9.41
CPU Address: 5a0, 5a1, 5a2
Accessed by CPU and serial interface (R/W)
C - CPUQOSC1 – CPU BYTE_C1 I
B - CPUQOSC2 – CPU BYTE_C2 I
A - CPUQOSC3 – CPU BYTE_C3 I
Represents values A-C for a CPU port. The values A-C are per-queue byte thresholds for random early drop.
QOSC3 represents A, and QOSC1 represents C. Granularity: 256 bytes
14.10
14.10.1
I
Accessed by CPU, serial interface and I
2
C Address F0, CPU Address:h600
(Group 6 Address) MISC Group
Bit [3:1]
Bits [0]:
Bits [7]:
Bits [6]:
Bits [5]:
Bit [4:0]:
CPUQOSC123
MII_OP0 – MII Register Option 0
7
hfc
6
1prst
Transmit Priority
Drop Priority
Half duplex flow control feature
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
Link partner reset auto-negotiate disable
Disable jabber detection. This is for HomePNA applications or any serial
operation slower than 10 Mbps.
0 = Enable
1 = Disable
Vendor specified link status register address (null value means don’t use it)
(Default 00). This is used if the Linkup bit position in the PHY is non-standard
5
DisJ
2
2
2
C Address h0C2, CPU Address 518)
C Address h0C3, CPU Address 519)
C Address h0C1, CPU Address 517)
4
Vendor Spc. Reg Addr
2
C (R/W)
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