ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 61

• Manufacturer Part Number: ZL50418GKC
• Description: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

When the CPU reads this register:
14.2.6
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When CPU reads this register
Interrupt sources (8 bits)
Address = 5 (read only)
Interrupt Register
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [7:3]:
Note: This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it.
Bit [5]:
Bit [6]:
Bit [7]:
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Set this bit to re-start the data that is sent from the CPU to Receive FIFO
(re-align). This feature can be used for software debug. For normal
operation must be '0'.
Do not use. Must be '0'
Reserved
Control Frame receive buffer ready, CPU can write a new frame
Control Frame transmit buffer1 ready for CPU to read
Control Frame transmit buffer2 ready for CPU to read
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Transmit FIFO End Of Frame (TXFIFO_EOF)
Reserve
Reserve
CPU frame interrupt
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU
to read
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU
to read
Gigabit port A interrupt
Gigabit port B interrupt
Reserve
- 1 – CPU can write a new control command 1
- 0 – CPU has to wait until this bit is 1 to write a new control command 1
- 1 – CPU can read a new control command 1
- 0 – CPU has to wait until this bit is 1 to read a new control command
- 1 – CPU can read a new control command 1
- 0 – CPU has to wait until this bit is 1 to read a new control command
Zarlink Semiconductor Inc.
ZL50418
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Data Sheet