ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 133

• Manufacturer Part Number: ZL50418GKC
• Description: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Notes:
# =Active low signal
Input = Input Signal
In-ST =Input signal with Schmitt-Trigger
Output = Output signal (Tri-State driver)
Out-OD = Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD = Input & Output signal with Open-Drain driver
E24
T26, R26
F26, E26
AE20, AJ18, AJ21,
AJ16, AJ14, AE14,
AJ12, AE11, AJ10,
AJ8, AE8, AJ6, AE5,
AJ4, AG1, AE1,
C21
C19, B19, A19
C20, B20, A20
Ball No(s)
TSTOUT15
G0_TXEN,
G0_TXER
G1_TXEN,
G1_TXER
M[15:0]_TXEN
P_D
OE_CLK[2:0]
LA_CLK[2:0]
Symbol
Zarlink Semiconductor Inc.
ZL50418
Default 1
Default: PCS
Default: PCS
Default: RMII
Must be pulled-down
Default: 111
Default: 111
133
I/O
SRAM Test Mode
0 – Enable test mode
1 – Normal operation
Giga0
Mode: G0_TXEN G0_TXER
Giga1
Mode: G1_TXEN G1_TXER
0 – GPSI
1 - RMII
Reserved - Must be pulled-down
Programmable delay for internal
OE_CLK from SCLK input. The
OE_CLK is used for generating the
OE0 and OE1 signals
Suggested value is 001.
Programmable delay for LA_CLK
and LB_CLK from internal OE_CLK.
The LA_CLK and LB_CLK delay
from SCLK is the sum of the delay
programmed in here and the delay in
P_D[15:13].
Suggested value is 011.
0
1
0
0
1
1
Description
0
1
1 RSVD
0
1
0
0
1
Data Sheet
0
1
GMII
RSVD
MII
GMII
PCS
MII
PCS