L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 18

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information
Table 1. Pin Descriptions (continued)
* Active-low signals within this document are indicated by an N following the symbol names.
18
18
Pin
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
CONTENDER
PCI_CBEN[0]
MPCIACTN
PCI_AD[8]
PCI_AD[7]
PCI_AD[6]
PCI_AD[5]
PCI_AD[4]
PCI_AD[3]
PCI_AD[2]
PCI_AD[1]
PCI_AD[0]
PCI_VIOS
Symbol*
LKON
PC2
PC1
PC0
V
V
LPS
V
V
V
V
SS
DD
SS
SS
DD
DD
(continued)
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
O
O
O
I
I
PCI Address/Data Bit.
Digital Ground.
Digital Power.
PCI Command/Byte Enable Signal (Active-Low).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
Digital Power.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Signaling Indicator. For PCI applications that use a universal
expansion board (see PCI Local Bus Specification, Rev. 2.2, Sec-
tion 4.1.1), connect this pin to the VI/O pin. For Cardbus applica-
tions, connect this pin to 3.3 V. For other cases, connect this pin to
3.3 V for PCI buses using 3.3 V signaling or to 5 V for PCI buses
using 5 V signaling.
Contender. On hardware reset (RESETN), this input sets the
default value of the CONTENDER bit indicated during SelfID. This
bit can be tied to V
manager or to ground (low) to not be considered for bus manager.
Power-Class Indicators. On hardware reset (RESETN), these
inputs set the default value of the power class indicated during
SelfID. These bits can be tied to V
required for particular power consumption and source characteris-
tics. In SelfID packet (see Section 4.3.4.1 of the 1394a-2000 Spec-
ification), PC0, the most significant bit of this 3-bit field,
corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corre-
sponds to bit 23. As an example, for a Power_Class value of 001,
PC0 = 0, PC1 = 0, and PC2 = 1.
Link On. Signal from the internal PHY core to the internal link core.
This signal is provided as an output for use in legacy power
management systems.
Link Power Status. Signal from the internal link core to the internal
PHY core. LPS is provided as an output for use in legacy power
management systems.
Mini PCI Function Active. An active-low output used only in Mini
PCI applications. A low indicates that the FW323 requires full
system performance. If MPCIACTN is low, the FW323 requires that
the system not be in a low-power state.
Digital Power.
DD
(high), so it will be considered for bus
Description
DD
(high) or to ground (low) as
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.