L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 5

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
FW323 06 1394a
December 2005
PCI PHY/Link Open Host Controller Interface
Table of Contents
(continued)
Table
Page
Table 35. Host Controller Control Register Description ......................................................................................... 48
Table 36. SelfID Buffer Pointer Register Description ............................................................................................ 50
Table 37. SelfID Count Register Description ......................................................................................................... 50
Table 38. Isochronous Receive Channel Mask High Register Description ........................................................... 51
Table 39. Isochronous Receive Channel Mask Low Register Description ............................................................ 51
Table 40. Interrupt Event Register Description ...................................................................................................... 52
Table 41. Interrupt Mask Register Description ...................................................................................................... 54
Table 42. Isochronous Transmit Interrupt Event Register Description .................................................................. 56
Table 43. Isochronous Transmit Interrupt Event Description ................................................................................ 57
Table 44. Isochronous Receive Interrupt Event Description ................................................................................. 58
Table 45. Fairness Control Register Description ................................................................................................... 59
Table 46. Link Control Register Description ......................................................................................................... 60
Table 47. Node Identification Register Description ............................................................................................... 61
Table 48. PHY Core Layer Control Register Description ...................................................................................... 62
Table 49. Isochronous Cycle Timer Register Description ..................................................................................... 62
Table 50. Asynchronous Request Filter High Register Description ....................................................................... 63
Table 51. Asynchronous Request Filter Low Register Description ....................................................................... 63
Table 52. Physical Request Filter High Register Description ................................................................................ 64
Table 53. Physical Request Filter Low Register Description ................................................................................. 64
Table 54. Asynchronous Context Control Register Description ........................................................................... 65
Table 55. Asynchronous Context Command Pointer Register Description ........................................................... 66
Table 56. Isochronous Transmit Context Control Register Description ................................................................ 67
Table 57. Isochronous Transmit Context Command Pointer Register Description ............................................... 68
Table 58. Isochronous Receive Context Control Register Description .................................................................. 69
Table 59. Isochronous Receive Context Command Pointer Register Description ................................................ 70
Table 60. Isochronous Receive Context Match Register Description ................................................................... 71
Table 61. FW323 Vendor-Specific Registers Description ..................................................................................... 72
Table 62. Isochronous DMA Control Registers Description .................................................................................. 72
Table 63. Asynchronous DMA Control Registers Description ............................................................................... 73
Table 64. Link Options Register Description ......................................................................................................... 74
Table 65. PHY Core Register Map ........................................................................................................................ 75
Table 66. PHY Core Register Fields ..................................................................................................................... 76
Table 67. PHY Core Register Page 0: Port Status Page ...................................................................................... 78
Table 68. PHY Core Register Port Status Page Fields ........................................................................................ 79
Table 69. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 80
Table 70. PHY Core Register Vendor Identification Page Fields .......................................................................... 80
Table 71. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 82
Table 72. NAND Tree Testing ............................................................................................................................... 85
Table 73. Absolute Maximum Ratings ................................................................................................................... 87
Table 74. Analog Characteristics ........................................................................................................................... 88
Table 75. Driver Characteristics ............................................................................................................................ 89
Table 76. Device Characteristics ........................................................................................................................... 89
Table 77. Switching Characteristics ...................................................................................................................... 90
Table 78. Clock Characteristics ............................................................................................................................. 90
Agere Systems Inc.
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