IDT72V8981J8 IDT, Integrated Device Technology Inc, IDT72V8981J8 Datasheet - Page 3

• Manufacturer Part Number: IDT72V8981J8
• Description: IC DGTL SW 128X128 44-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V8981J8

• Circuit: 1 x 4:4
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V8981J8

PIN DESCRIPTIONS
SYMBOL
IDT72V8981 3.3V Time Slot Interchange
Digital Switch 128 x 128
GND
V
DTA
RX0-3
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-3
ODE
CC
Ground.
V
Data Acknowledgment
(Open Drain)
RX Input 0 to 3
Frame Pulse
Clock
Address 0 to 5
Data Strobe
Read/Write
Chip Select
Data Bus 0 to 7
TX Outputs 0 to 3
(Three-state Outputs)
Output Drive Enable
CC
NAME
I/O
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
O
O
I
I
I
I
I
I
I
I
Active LOW input enabling a microprocessor read or write of control register or internal memories.
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is
Ground Rail.
+3.3 Volt Power Supply.
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input identifies frame synchronization signals formatted to ST-BUS
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT72V8981 internal registers.
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Connection Memory LOW and data memory.
HIGH, each channel may still be put into high-impedance by software control.
3
DESCRIPTION
Commercial Temperature Range
®
specifications.