IDT72V8981J8 IDT, Integrated Device Technology Inc, IDT72V8981J8 Datasheet - Page 5

• Manufacturer Part Number: IDT72V8981J8
• Description: IC DGTL SW 128X128 44-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V8981J8

• Circuit: 1 x 4:4
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V8981J8

INITIALIZATION OF THE IDT72V8981
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
TABLE 1 — INPUT STREAM TO OUT-
PUT STREAM COMBINATIONS THAT
CAN
2-CHANNEL DELAY
IDT72V8981 3.3V Time Slot Interchange
Digital Switch 128 x 128
On initialization or power up, the contents of the Connection Memory High
Input
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
0
1
PROVIDE
Channel 0
Channel 0
Channel 0
Channel 0
10000
0
Control Register
Connection Memory High
Channel 1
Channel 1
Channel 1
Channel 1
10000
1
Connection Memory Low
THE
Output Stream
1,2,3
Data Memory
3
Channel 2
Channel 2
Channel 2
Channel 2
10001
0
CR
MINIMUM
b
7

Figure 3. Address Mapping
CR
b
CR
6 CR
0
1
1
b
4 CR
b
5 CR
5
1
0
1
b
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
TABLE 2 — ADDRESS MAPPING
3
A5 A4 A3 A2 A1 A0
0
1
1
1
1
1
1
During the microprocessor initialization routine, the microprocessor should
b
4 CR
Channel 31
Channel 31
Channel 31
Channel 31
11111
1
X
0
0
1
•
•
•
b
X
0
0
1
•
•
•
3 CR
X
0
0
1
•
•
•
b
2 CR
0
0
0
1
•
•
•
External Address Bits
0
0
1
1
•
•
•
b
1 CR
HEX ADDRESS
Commercial Temperature Range
b
00-1F
0
3F
CR
20
21
•
•
•
0
0
1
1
b
1 CR
A5-A0
0
1
0
1
b
0
Control Register
5702 drw07
Channel 31
Stream
Channel 0
Channel 1
LOCATION
0
1
2
3
•
•
•
(2)
(2)
(2)
(1)