W224BH Cypress Semiconductor Corporation., W224BH Datasheet

W224BH

Manufacturer Part Number

W224BH

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.W224BH.pdf (18 pages)

2.W224BH.pdf (18 pages)

Specifications of W224BH

Case

SSOP/56

Date_code

02+

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Features

Key Specifications

CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps

Intel is a registered trademark of Intel Corporation.

Cypress Semiconductor Corporation

Document #: 38-07191 Rev. *A

• Maximized EMI suppression using Cypress’s Spread

• Single chip system FTG for Mobile Intel

• Three CPU outputs

• Seven copies of PCI clock (one Free Running)

• Seven SDRAM clock (one DCLK for Memory Hub)

• Two copies of 48-MHz clock (non-spread spectrum) op-

• Three 3V66 Hublink/AGP outputs

• One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)

• Two APIC outputs

• One buffered reference output

• Supports frequencies up to 133 MHz

• Supports 5% and 10% overclocking

• SMBus interface for programming

• Power management control inputs

Block Diagram

PWR_DWN#

PCI_STP#

CPU_STP#

Spectrum technology (–0.5% and –1.0%)

timized for USB reference input and video DOT clock

SDATA

SCLK

FS0:1

133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms

PLL 1

PLL2

SMBus

Logic

XTAL

OSC

Network

Divider

PLL Ref Freq

Control

Clock

Stop

Control

Clock

Stop

•

3901 North First Street

Platforms

VDD_48MHz

VDD_3V66

3V66_0:1

VDD_SDRAM

SDRAM0:5

3V66_AGP

USB (48MHz)

DOT (48MHz)

VDD_REF

REF

VDD_CPU

CPU0

DCLK

VDD_APIC

APIC0:1

VDD_PCI

VCH_CLK

CPU_F1:2

PCI_F

PCI1:6

APIC, 48-MHz, 3V66, PCI Outputs

Cycle-to-Cycle Jitter: ...................................................500 ps

CPU Output Skew: ......................................................150 ps

3V66 Output Skew: .....................................................175 ps

APIC, SDRAM Output Skew: ......................................250 ps

PCI Output Skew:........................................................500 ps

VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: .......... 3.3V±5%

VDDQ2 (CPU, APIC):.............................................. 2.5V±5%

Table 1. Pin Selectable Functions

TEST#

GND_48MHz

VDD_48MHz

Pin Configuration

GND_CORE

VDD_CORE

GND_3V66

*PCI_STP#

3V66_AGP

VDD_3V66

GND_REF

Note:

VDD_REF

GND_PCI

VDD_PCI

•

3V66_0

3V66_1

PCI_F

Internal pull-up resistors present on inputs marked with [*].

Design should not rely solely on internal pull-up to set I/O pins

HIGH.

San Jose

PCI1

PCI2

PCI3

PCI4

PCI5

PCI6

DOT

REF

USB

FS0

FS1

•

FS0

[ 1 ]

CA 95134

Revised December 22, 2002

Three-state

100 MHz

133 MHz

66 MHz

CPU

Test

•

GND_APIC

APIC0

APIC1

VDD_APIC

CPU0

VDD_CPU

CPU_F1

CPU_F2

GND_CPU

GND_SDRAM

SDRAM0

SDRAM1

VDD_SDRAM

SDRAM2

SDRAM3

GND_SDRAM

SDRAM4

SDRAM5

DCLK

VDD_SDRAM

VCH_CLK

VDD_VCH

CPU_STP#*

TEST#*

PWR_DWN#*

SCLK

SDATA

FS1

408-943-2600

Three-state

W224B

100 MHz

133 MHz

100 MHz

SDRAM

Test

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