PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet
PC87200VUL160A
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PC87200VUL160A Summary of contents
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PC87200 PCI to ISA Bridge 1.0 General Description The PC87200 Enhanced Integrated PCI-to-ISA bridge works with an LPC chipset to provide ISA slot support complement to the National Semiconductor PC8736x Super I/O family. 2.0 Features 2.1 General ...
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Table of Contents 1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 Features . . . ...
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Device Overview The PC87200 can be described as providing the functional blocks shown in Figure 1. — PCI bus master/slave interface — ISA bus master/slave interface — Serial IRQ slave mode interface — PROHIBIT signal support — PC/PCI DMA ...
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Device Overview (Continued) Timing of the serialized IRQ is illustrated as follows. START CYCLE START PCI CLK SERIRQ START Driving Slave (Q) Source Master ( Recovery; T= Turn-around Sample IRQ15 S R PCI CLK SERIRQ ...
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Device Overview (Continued) Table 1. SERIRQ Slave Generation Periods SERIRQ Signal Generated Period 1 Reserved. 2 Reserved. 3 Reserved. 4 IRQ3 5 IRQ4 6 IRQ5 7 IRQ6 8 IRQ7 9 Reserved. 10 IRQ9 11 IRQ10 12 IRQ11 13 IRQ12 ...
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Device Overview (Continued) When a legacy ISA bus DMA request is asserted, the PC87200 will transmit that request to the PC/PCI Primary Bus Arbiter by encoding it and driving it out the PC87200’s PCPCIREQ# according to the above; first ...
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Device Pinout Vdd 1 Vss 2 SA18 3 SA19 4 IRQ9 5 DACK2# 6 DREQ2 7 SYSCLK 8 SD7 9 SD6 10 SD5 11 SD4 12 IOCHK# 13 REFRESH# 14 SD3 15 SD2 16 SD1 17 SD0 18 Vdd ...
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Pin Descriptions 5.1 Signal Definitions This section defines the signals and describes the external interface of the PC87200. The following diagram shows the pins organized by their functional groupings. Internal test and electrical pins are not shown. Serialized SERIRQ ...
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Pin Descriptions (Continued) 5.2 Pin Assignments The tables in this section use several common abbreviations. Table 2. lists the mnemonics and their meanings. In the next section, description of each signal within its associated functional group is provided. Mnemonic ...
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Pin Descriptions (Continued) 5.3.3 PCI Interface Signals Signal Name Pin No. Type AD[31:0] 65,66, I/O 67,68, t/s 69,70, 73,74, 77,78, 81,82, 83,84, 85,86, 100,101, 102,103, 104,107, 108,109, 111,112, 115,116, 117,118, 119,120 C/BE[3:0]# 75,87, I/O 99,110 t/s IDSEL 76 I ...
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Pin Descriptions (Continued) Signal Name Pin No. Type DEVSEL# 93 I/O t/s PAR 96 I/O t/s SERR Description PCI Device Select DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and subtractive ...
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Pin Descriptions (Continued) 5.3.4 ISA Bus Interface Signals Signal Name Pin No. Type MASTER SA[23:0] 33,32, I/O 31,30, 4,3,160, 159,158, 157,156, 155,154, 153,152, 149,148, 147,146, 145,144, 143,142, 141 SD[15:0] 56,55, I/O 54,53, 50,49, 48,47, 9,10, 11,12, 15,16, ...
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Pin Descriptions (Continued) Signal Name Pin No. Type IOCS16 IOR# 25 I/O IOW# 26 I/O MEMCS16# 28 I/O OD MEMR# 43 I/O MEMW# 44 I/O AEN 23 O IRQ[15:14], [12:9], 37,38, I [7:3] 36,35, 34,5, 132,131, 130,129, ...
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Pin Descriptions (Continued) 5.3.6 PC/PCI signals PCPCIREQ# 125 O PCPCIGNT# 126 I 5.3.7 Power, Ground, and Reserved Terminals Signal Name Pin No. Type VDD 1,19,39, PWR 59,71, 79,89, 97,105, 113,121, 139,150 VSS 2,20,40, GND 60,72, 80,90, 98,106, 114,122, 140,151 ...
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Configuration a. Connect the NOGO signal of the south bridge to Prohibit pin of PC87200, SERIRQ to SERIRQ, REQ[A] to PCPCIREQ#, GNT[A] to PCPCIGNT# (other PC/PCI REQ, GNT pair may also be used). If BPD# is not being used, ...
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Register Descriptions The 87200 is a single function device. Its register space is called the Bridge Configuration Registers Space (F0) which is accessed through the PCI interface using the PCI Type One Configuration Mechanism. The PCI header is a ...
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Register Descriptions 7.2 Chipset Register Space The Chipset Register Space of the PC87200 is comprised of one function with PCI header registers. There is no memory or I/O mapped register. 7.2.1 Bridge Configuration Registers - Function 0 The register ...
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Register Descriptions Table 4. Bridge Configuration Registers (Continued) Bit 8 Data Parity Detected —This bit is set when: 1) The PC87200 asserted PERR# or observed PERR# asserted. 2) PC87200 is the master for the cycle in which the PERR# ...
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Register Descriptions Table 4. Bridge Configuration Registers (Continued) Bit Index 41h 7 Burst to Beat — Bursts are converted to single beats for X-Bus to PCI bus reads Disable Enable. 6 Internal use, do not ...
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Register Descriptions Table 4. Bridge Configuration Registers (Continued) Bit 6 Internal use, do not overwrite. 5 Internal use, do not overwrite. 4 Internal use, do not overwrite. 3 Internal use, do not overwrite. 2 Internal use, do not overwrite. ...
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Register Descriptions Table 4. Bridge Configuration Registers (Continued) Bit Index 53h-5Ah Index 5Bh 7 Internal use, do not overwrite. 6 Reserved — Set BIOS ROM Positive Decode — Selects positive or subtractive decoding for accesses to ...
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Electrical Characteristics 8.1 Electrical Specifications This section provides information on testing modes, electrical connections, absolute maximum ratings, recommended operating conditions, and DC/AC characteristics. All voltage values in Electrical Specifications are with respect to V unless otherwise noted. For detailed ...
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Electrical Characteristics 8.2.1 Test Mode Logic This block will produce various test mode signals for differ- ent test modes : — NAND test signal pad_pcirstx_in irq3 irq4 irq6 irq7 test_in irq3 irq4 irq5 irq6 test_in irq3 irq4 irq5 irq6 ...
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Electrical Characteristics 8.2.2 NAND Tree Connections During NAND tree testing, all outputs and bi-directional pins will be tri-stated except BALE and RSTDRV pins. The first input of the NAND chain is SA18. The NAND chain is routed counter-clockwise around ...
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Electrical Characteristics 8.2.3 NAND Tree Order Pin # Pin Name 1 VDD 2 VSS 3 SA18 first input in NAND chain 4 SA19 5 IRQ9 6 DACK2# 7 DREQ2 8 SYSCLK 9 SD7 10 SD6 11 SD5 12 SD4 ...
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Electrical Characteristics Pin # Pin Name 74 AD24 75 C/BE3# 76 IDSEL 77 AD23 78 AD22 79 VDD 80 VSS 81 AD21 82 AD20 83 AD19 84 AD18 85 AD17 86 AD16 87 C/BE2# 88 FRAME# 89 VDD 90 ...
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Electrical Characteristics Pin # Pin Name 147 SA6 148 SA7 149 SA8 150 VDD 151 VSS 152 SA9 153 SA10 154 SA11 155 SA12 156 SA13 157 SA14 158 SA15 159 SA16 160 SA17 end of NAND chain Note ...
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Electrical Characteristics 8.2.4 Timing Diagram for NAND test Set PCIRST#, BALE and IRQ7 to low (PCPCIREQ# should be left floating), toggle PCICLK (provide a low-to- high transition) at least once (recommended to provide two edges as show in the ...
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Electrical Characteristics 8.3 Electrical Connections 8.3.5 Unused Input Pins All inputs not used by the system designer should be kept at either ground prevent possible spurious oper- DD. ation, connect active-high inputs to ground through a ...
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Electrical Characteristics 8.6 DC Characteristics Table 8. DC Characteristics (at Recommended Operating Conditions) Symbol Parameter ISA bus (including PROHIBIT, BPD#) V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage ...
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Electrical Characteristics 8.7 AC Characteristics The following tables list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. The rising-clock-edge reference level V Input or output signals must cross these levels during ...
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Electrical Characteristics Symbol Parameter Input Signal t PCICLK Cycle Time cyc t PCICLK High Time HIGH t PCICLK Low Time LOW -- PCICLK Slew Time Note 1: Rise and fall times are specified in terms of the edge rate ...
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Physical Dimensions 160 Lead Molded Plastic Quad Flat Package (JEDEC) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL ...