PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet - Page 13

• Manufacturer Part Number: PC87200VUL160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: NSC [National Semiconductor]

5.0 Pin Descriptions
5.3.5 Miscellaneous Signals (Continued)
IOCS16#
IOR#
IOW#
MEMCS16#
MEMR#
MEMW#
AEN
IRQ[15:14], [12:9],
[7:3]
DREQ[7:5],
DREQ[3:0]
DACK[7:5]#,
DACK[3:0]#
TC
IOCHK#
SERIRQ
PROHIBIT
BPD#
Signal Name
Signal Name
132,131,
130,129,
7,137,42
6,136,41
Pin No.
Pin No.
46,134,
45,133,
37,38,
36,35,
58 52,
57,51,
34,5,
128
127
138
29
25
26
28
43
44
23
63
13
64
(Continued)
Type
Type
s/t/s
OD
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I/O Chip Select 16
IOCS16# is asserted by 16-bit ISA I/O devices based on an asynchronous de-
code of SA[15:0] to indicate that SD[15:0] may be used to transfer data (8-bit ISA
I/O devices use SD[7:0]).
I/O Read
IOR# is asserted to request an ISA I/O slave to drive data onto the data bus.
I/O Write
IOW# is asserted to request an ISA I/O slave to accept data from the data bus.
Memory Chip Select 16
MEMCS# is asserted by 16-bit ISA memory devices based on an asynchronous
decode of SA[23:17] to indicate that SD[15:0] may be used to transfer data (8-
bit ISA memory devices use SD[7:0]).
Memory Read
MEMR# is asserted for all memory read accesses (including those above 1MB).
It enables 16-bit memory slaves to decode the memory address on SA[23:0].
Memory Write
MEMW# is asserted for all memory write accesses (including those above 1MB).
It enables 16-bit memory slaves to decode the memory address on SA[23:0].
Address Enable
AEN asserted indicates to ISA memory devices that a valid address for a DMA
transfer is present on SA[23:0], and for I/O devices to ignore this address and
any data on the ISA bus.
ISA Bus Interrupt Request
IRQ inputs are interrupts that indicate ISA devices or other devices requesting a
CPU interrupt service.
DMA Request - Channels [7:5], [3:0]
DREQ inputs are asserted by ISA DMA devices to request a DMA transfer. The
request must remain asserted until the corresponding DACK# is asserted.
DMA Acknowledge- Channels [7:5], [3:0]
DACK# outputs are asserted to indicate when a DREQ is granted and the start
of a DMA cycle.
Terminal Count
TC signals the final data transfer of a DMA transfer.
I/O channel check
Asserted by an ISA device indicating an error condition.
Serial IRQ
This is a one pin bus that conveys interrupt source information to the chipset.
PROHIBIT
An active high signal from the chipset indicating that the PC87200 should not act
as the subtractive decode agent on the PCI bus.
BIOS Positive Decode (active low)
When this pin is asserted low after BALE is detected high after reset, the PRO-
HIBIT signal will be a don’t care. The BIOS memory range will be positively de-
coded and claimed as such. All other cycles are still subtractively decoded.
13
Description
Description
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