PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet - Page 19

• Manufacturer Part Number: PC87200VUL160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: NSC [National Semiconductor]

7.0 Register Descriptions
Index 41h
Index 42h
Index 43h
Index 44h
2:1
Bit
7
6
5
4
3
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Burst to Beat — Bursts are converted to single beats for X-Bus to PCI bus reads: 0 = Disable; 1 = Enable.
Internal use, do not overwrite
PERR# Signals SERR# — Assert SERR# any time that PERR# is asserted or detected active by the
PC87200 (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 =
Enable.
Write Buffer Enable — Allow 16-byte buffering for X-Bus to PCI bus writes: 0 = Disable; 1 = Enable.
Internal use, do not overwrite.
Subtractive Decode — These bits determine the point at which the PC87200 accepts cycles that are not
claimed by another device. The PC87200 defaults to taking subtractive decode cycles in the default cycle
clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or me-
dium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded
subtractively.
00 = Default sample (4th clock from FRAME# active)
01 = Slow sample (3rd clock from FRAME# active)
1x = No subtractive decode
Internal use, do not overwrite.
Internal use, do not overwrite
Internal use, do not overwrite.
Delayed Transactions — Allow delayed transactions on the PCI bus: 0 = Disable; 1 = Enable.
Internal use, do not overwrite.
No X-Bus ARB, Buffer Enable — When PC87200 is a PCI target, allow buffer PCI transactions without X-Bus
arbitration: 0 = Disable; 1 = Enable.
Internal use, do not overwrite.
Internal use, do not overwrite.
Internal use, do not overwrite.
Reserved — Set to 0.
Internal use, do not overwrite.
Internal use, do not overwrite.
Internal use, do not overwrite.
Internal use, do not overwrite.
Internal use, do not overwrite.
PCI Retry Cycles — When PC87200 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry
cycles:
0 = Disable; 1 = Enable.
This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be
valid.
Internal use, do not overwrite.
Internal use, do not overwrite.
Table 4. Bridge Configuration Registers (Continued)
(Continued)
PCI Function Control Register 2 (R/W)
PCI Function Control Register 3 (R/W)
PCI Function Control Register 4
Reset Control Register (R/W)
19
Description
Reset Value = 00000000b
Reset Value = 10h
Reset Value = 28h
Reset Value = 46h
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