PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet - Page 18

• Manufacturer Part Number: PC87200VUL160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: NSC [National Semiconductor]

7.0 Register Descriptions
Index 08h
Index 09h-0Bh
Index 0Ch
Index 0Dh
Index 0Eh
Index 0Fh
Index 10h-3Fh
Index 40h
Note: Bits 6 and 5 emulate the behavior of first generation devices developed for PCI.
6:0
7:0
7:4
3:0
7:0
7:0
2:1
Bit
8
7
7
6
5
4
3
0
Data Parity Detected —This bit is set when:
1) The PC87200 asserted PERR# or observed PERR# asserted.
2) PC87200 is the master for the cycle in which the PERR# occurred, and PE is set (F0 Index 04h[6] = 1).
Write 1 to clear.
Fast Back-to-Back Capable — As a target, PC87200 is capable of accepting fast back-to-back transactions:
0 = Disable; 1 = Enable. This bit is always set to 1.
Reserved — Set to 0.
PCI Cache Line Size Register — reserved.
Reserved — Set to 0.
PCI Latency Timer Value — The PCI Latency Timer Register prevents system lockup when a slave does not
respond to a cycle that the PC87200 masters. If the value is set to 00h (default), the timer is disabled. If the
timer is written with any other value, bits [3:0] become the four most significant bytes in a timer that counts
PCI clocks for slave response. The timer is reset on each valid data transfer. If the counter expires before the
next assertion of TRDY# is received, the PC87200 stops the transaction with a master abort and asserts
SERR#, if enabled to do so.
PCI Header Type Register — This.register defines the format of this header. This header is of type format 0.
Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).
Reserved. Set to 0.
Single Write Mode — PC87200 accepts only single cycle write transfers as a slave on the PCI bus and per-
forms a target disconnect with the first data transferred: 0 = Disable (accepts burst write cycles); 1 = Enable.
Single Read Mode — PC87200 accepts only single cycle read transfers as a slave on the PCI bus and per-
forms a target disconnect with the first data transferred. 0 = Disable (accepts burst read cycles); 1 = Enable.
Retry PCI Cycles — Retry inbound PCI cycles if data is buffered and waiting to go outbound on PCI:
0 = No Retry; 1 = Retry.
Write Buffer — PCI slave write buffer: 0 = Disable; 1 = Enable.
Reserved- set to 0.
BS8/16 — This bit can not be written. Always = 1.
Internal use, do not overwrite.
Table 4. Bridge Configuration Registers (Continued)
(Continued)
PCI Function Control Register 1 (R/W)
PCI Cache Line Size Register (R/W)
PCI Latency Timer Register (R/W)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI BIST Register (RO)
PCI Header Type (RO)
Reserved
18
Description
Reset Value = 060100h
Reset Value = 00h
Reset Value = 00h
Reset Value = 00h
Reset Value = 00h
Reset Value = 00h
Reset Value = 79h
Reset Value =00h
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