K4T51043QB-GCCC SAMSUNG [Samsung semiconductor], K4T51043QB-GCCC Datasheet - Page 19

• Manufacturer Part Number: K4T51043QB-GCCC
• Description: 512Mb B-die DDR2 SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read command
Exit active power down to read command
Exit active power down to read command
(slow exit, lower power)
512Mb B-die DDR2 SDRAM
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
Symbol
Page 19 of 28
min(tCL, tCH)
tHP - tQHS
tRFC + 10
2* tACmin
WR+tRP
tAC min
6 - AL
3750
-0.25
min
0.45
0.45
0.35
0.35
37.5
-500
-450
225
100
0.35
375
250
200
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
10
50
15
x
2
2
2
x
x
2
DDR2-533
tAC max
tAC max
tAC max
max
+500
+450
8000
0.55
0.55
0.25
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
min(tCL, tCH)
tHP - tQHS
2* tACmin
tRFC + 10
WR+tRP
tAC min
6 - AL
5000
-0.25
min
-600
-500
0.45
0.45
0.35
0.35
0.35
37.5
275
150
0.35
475
350
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
15
10
2
2
2
x
x
x
2
DDR2-400
tAC max
tAC max
tAC max
max
+600
+500
0.55
0.55
8000
0.25
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DDR2 SDRAM
Rev. 1.5 July 2005
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
15,16,17,20
15,16,17,21
14,16,18,23
14,16,18,22
Notes
20,21
9, 10
24
27
27
22
21
19
28
28
12
12
23
33
11
9