K4T51043QB-GCCC SAMSUNG [Samsung semiconductor], K4T51043QB-GCCC Datasheet - Page 20

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K4T51043QB-GCCC

Manufacturer Part Number
K4T51043QB-GCCC
Description
512Mb B-die DDR2 SDRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
CKE minimum pulse width (high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE asynchronously
drops LOW
512Mb B-die DDR2 SDRAM
Parameter
t
t
t
t
t
t
t
tANPD
tAXPD
tOIT
tDelay
CKE
AOND
AON
AONPD
AOFD
AOF
AOFPD
Symbol
Page 20 of 28
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
min
2.5
3
2
3
8
0
DDR2-533
tAC(max)+ 0.6
tAC(max)+1
tAC(max)+1
2tCK+tAC
(max)+1
2.5tCK+
max
2.5
12
2
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
min
2.5
3
2
3
8
0
DDR2-400
tAC(max)+ 0.6
tAC(max)+1
tAC(max)+1
2tCK+tAC
(max)+1
2.5tCK+
max
2.5
12
2
DDR2 SDRAM
Rev. 1.5 July 2005
Units
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
Notes
13, 25
36
26
24

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