HYS64D128320GU-6-B INFINEON [Infineon Technologies AG], HYS64D128320GU-6-B Datasheet
HYS64D128320GU-6-B
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HYS64D128320GU-6-B Summary of contents
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HYS64D64300[G/H]U–[5/6]–B HYS72D64300[G/H]U–[5/6]–B HYS64D128320[G/H]U–[5/6]–B HYS72D128320[G/H]U–[5/6]– ...
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Edition 2004-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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HYS64D64300[G/H]U–[5/6]–B HYS72D64300[G/H]U–[5/6]–B HYS64D128320[G/H]U–[5/6]–B HYS72D128320[G/H]U–[5/6]– ...
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... HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B Revision History: Rev. 1.0 Previous Version: Rev. 0.5 Page Subjects (major changes since last revision) 7 Added Non-Green Modules DDR400 & DDR333 and removed DDR266 8,12ff editorial changes 22,23 Updated 24,27,30,33 Update SPD Codes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document ...
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... Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules 5 Rev. 1.0, 2004-05 ...
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... Overview 1.1 Features • 184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Workstation main memory applications One rank 64M x 64, 64M ×72 and two ranks 128M × 64, 128M ×72 organization • • JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply • ...
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... HYS72D128320GU–5–B PC3200U–30330–B0 PC2700 (CL=2.5) HYS64D64300GU–6–B PC2700U–25330–A0 HYS72D64300GU–6–B PC2700U–25330–A0 HYS64D128320GU–6–B PC2700U–25330–B0 HYS72D128320GU–6–B PC2700U–25330–B0 PC3200 (CL=3.0) HYS64D64300HU–5–B PC3200U–30330–A0 HYS72D64300HU–5–B PC3200U– ...
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... SSTL I SSTL I SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC – Note: 128 Mbit module I SSTL Address Signal 13 Note: 1 Gbit module NC – Note: Module based on 512 Mbit smaller dies I/O SSTL Data Bus 63:0 I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O SSTL ...
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... Check Bit 3 Note: ECC type module Note: Non-ECC module Check Bit 4 Note: ECC type module Note: Non-ECC module Check Bit 5 Note: ECC type module Note: Non-ECC module Check Bit 6 Note: ECC type module Note: Non-ECC module Check Bit 7 Note: ECC type module ...
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... I SSTL 159 DM5 I SSTL 169 DM6 I SSTL 177 DM7 I SSTL 140 DM8 I SSTL Data Mask 8 Note: ECC type module NC NC – Note: Non-ECC module EEPROM 92 SCL I CMOS Serial Bus Clock 91 SDA I/O OD Serial Bus Data 181 SA0 I CMOS Slave Address Select Bus 2:0 ...
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... Pin 171 - Pin 175 - Pin 179 - Pin 183 11 Unbuffered DDR SDRAM Modules Pin Configuration Abbreviations for Buffer Type Serial Stub Terminated Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR ...
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... DQ42 I/O 2 DQ43 I/O 3 DQ44 I/O 4 DQ45 I/O 5 DQ46 I/O 6 DQ47 I/O 7 Ω ± Table Ω ± Clock Input CK0, CK0 CK1, CK1 CK2, CK2 12 Unbuffered DDR SDRAM Modules Pin Configuration # of row/bank/ Refresh Period Interval columns bits 13/2/ 13/2/ 13/2/ 13/2/ SPD EEPROM ...
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... I/O 7 DQ63 SCL SAD SA0 SA1 SA2 Table 8 Clock Input Ω ± Ω ± CK0, CK0 5 % CK1, CK1 CK2, CK2 13 Unbuffered DDR SDRAM Modules Pin Configuration V : SPD EEPROM SDRAMs D0 - D15 DD DDQ V : SDRAMs D0 - D15 REF V : SDRAMs D0 - D15 SS Strap: see Note 1 D4 ...
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... A0 SA1 A1 SA2 Ω ± Table Ω ± Clock Input CK0, CK0 CK1, CK1 CK2, CK2 14 Unbuffered DDR SDRAM Modules Pin Configuration V : SPD EEPROM SDRAMs DDQ V : SDRAMs REF V : SDRAMs Strap: see Note 1 D3 ...
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... DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM8/DQS17 : SDRAMs D0 - D17 Ω ± Table Ω ± Clock Input CK0, CK0 CK1, CK1 CK2, CK2 15 Unbuffered DDR SDRAM Modules Pin Configuration SCL SCL SAD SAD SA0 A0 SA1 A1 SA2 DQS4 DQS ...
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... DRAM Loads R = 120 ± 5% DIMM Connector 1 DRAM Loads R = 120 ± 5% DIMM Connector Figure 6 Clock Net Wiring Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules DRAM1 DRAM2 DRAM3 4 DRAM Loads DRAM4 DRAM5 R = 120 ± 5% DRAM6 DIMM Connector DRAM1 Cap. DRAM3 Cap ...
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... V V DDQ DDQ DDQ V V – 0.04 REF REF 0.15 REF DDQ V –0.3 REF V –0.3 DDQ V 0.36 DDQ 0.71 1.4 17 Unbuffered DDR SDRAM Modules Electrical Characteristics Values Unit Note/ Test Condition typ. max. – – DDQ 0.5 – +3.6 V – – +3.6 V – – +3.6 V – °C – ...
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... 7 0.4 — 0.4 — 2.2 — IPW 18 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit Note/Test Condition µA Any input 0 V ≤ All other pins not under test 8) µA DQs are disabled ≤ ≤ OUT DDQ ...
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... Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules Symbol –5 –6 DDR400B DDR333 Min. Max. Min. t 1.75 — ...
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... WTR t 75 — XSNR t 200 — XSRD t — 7.8 REFI = +2.5 V ± 0.2 V (DDR333 CK/CK slew rate are ≥ 1.0 V/ns. V REF V stabilizes. REF V . IL(ac) 20 Unbuffered DDR SDRAM Modules Electrical Characteristics –6 Unit Note/ Test Condition DDR333 Min. Max. 2)3)4)5) 12 — ns 2)3)4)5) 15 — ns 2)3)4)5)11 2)3)4) — CK 2)3)4)5) 75 — ...
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... IN REF or ≤ IH,MIN IL,MAX for DQ, DQS and DM. ILMAX IN REF IH,MIN RC RAS,MAX OUT 21 Unbuffered DDR SDRAM Modules Electrical Characteristics V = for DQ, DQS and DM. REF Rev. 1.0, 2004-05 10042003-RYU3-RQON Symbol I DD0 I DD1 I DD2P I DD2F I DD2Q I DD3P I DD3N I DD4R I DD4W I DD5 I DD6 ...
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... DDx m × [component × DDx DD3N modules I currents are not included into calculations: module DDQ load conditions I 5) The module values are calculated from the corrponent DDx Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B 512MB 1GB × ...
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... DDx m × [component × DDx DD3N modules I currents are not included into calculations: module DDQ load conditions I 5) The module values are calculated from the corrponent DDx [ Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B 512MB 1 GB × ...
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... C1 60 -0.5 [ns Unbuffered DDR SDRAM Modules SPD Contents 512 MB 1 GByte 1 GByte ×72 ×64 ×72 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8) Rev 0.0 Rev 0.0 Rev 0.0 HEX HEX HEX ...
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... Organization Label Code JEDEC SPD Revision Byte# Description t 26 SDRAM @ CL AC max t 27 [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank t 32 tCS [ns] AS tCH [ns] AH [ns [ns not used t 41 [ns] RCmin t 42 [ns] RFCmin ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( 127 not used Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules 512 MB 512 MB 1 GByte ×64 ×72 × ...
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... C1 60 -0.5 [ns [ns Unbuffered DDR SDRAM Modules SPD Contents 512 MB 1 GByte 1 GByte ×72 ×64 ×72 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8) Rev 0.0 Rev 0.0 Rev 0.0 HEX HEX HEX ...
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... SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank t 32 tCS [ns] AS tCH [ns] AH [ns [ns not used t 41 [ns] RCmin t ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( 127 not used Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules 512 MB 512 MB 1 GByte ×64 ×72 × ...
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... C1 75 -0.5 [ns [ns Unbuffered DDR SDRAM Modules SPD Contents 512 MB 1 GByte 1 GByte ×72 ×64 ×72 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8) Rev 0.0 Rev 0.0 Rev 0.0 HEX HEX HEX ...
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... SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank [ns] AS [ns] AH [ns [ns not used t ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( 127 not used Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules 512 MB 512 MB 1 GByte ×64 ×72 × ...
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... C1 75 -0.5 [ns [ns Unbuffered DDR SDRAM Modules SPD Contents 512 MB 1 GByte 1 GByte ×72 ×64 ×72 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8) Rev 0.0 Rev 0.0 Rev 0.0 HEX HEX HEX ...
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... SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank [ns] AS [ns] AH [ns [ns not used t ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( 127 not used Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B Unbuffered DDR SDRAM Modules 512 MB 512 MB 1 GByte ×64 ×72 × ...
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... Package Outlines 1 1 2.36 ±0.1 ø0 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 7 Raw Card A DDR UDIMM HYS64D64300HU-[5/6/7]-B (1 Rank Module) Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B 133.35 128.95 A 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0.1 0 Unbuffered DDR SDRAM Modules ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 8 Raw Card A DDR UDIMM HYS72D64300HU-[5/6/7F]-B (1 Rank Module) Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 Unbuffered DDR SDRAM Modules ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 9 Raw Card B DDR UDIMM HYS64D128320HU-[5/6/7]-B (2 Ranks Module) Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B 133.35 128.95 A 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 Unbuffered DDR SDRAM Modules Package Outlines ...
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... 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 10 Raw Card B DDR UDIMM HYS72D128320HU-[5/6/7/-B (2 Rank Module) Data Sheet HYS[64/72]D[64300/128320][G/H]U–[5/6]–B 133.35 128. 6.62 2.175 6. 1.27 = 120.65 1.8 ±0 Unbuffered DDR SDRAM Modules Package Outlines 0 ...
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Published by Infineon Technologies AG ...