GS8644Z18E-166I GSI [GSI Technology], GS8644Z18E-166I Datasheet
GS8644Z18E-166I
Related parts for GS8644Z18E-166I
GS8644Z18E-166I Summary of contents
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... The GS8644Z18/36E-xxxV is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. ...
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Bump BGA—x18 Common I/O—Top View DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G NC DQB ...
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Bump BGA—x36 Common I/O—Top View DQPC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G DQC DQC ...
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GS8644Z18/36E-xxxV 165-Bump BGA Pin Description Symbol Type I — ...
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... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
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Pipelined and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.05 6/2006 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.05 6/2006 Specifications cited are subject to change without notice. For latest documentation see ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Rev: 1.05 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15/30 Preliminary GS8644Z18/36E-xxxV © 2003, GSI Technology ...
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AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...
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Write A Read CKE ADV Rev: 1.05 6/2006 Specifications cited are subject to change without notice. For latest documentation ...
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Write A Write CKE ADV A0– D(A) G *Note High(False ...
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JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS input is sampled ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in ...
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SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into ...
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JTAG TAP Instruction Set Summary Instruction Code EXTEST 000 Places the Boundary Scan Register between TDI and TDO. IDCODE 001 Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between ...
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JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version) Parameter 1.8 V Test Port Input Low Voltage 2.5 V Test Port Input Low Voltage 1.8 V Test Port Input High Voltage 2.5 V Test Port Input High Voltage ...
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... TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time ...
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Rev: 1.05 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 26/30 Preliminary GS8644Z18/36E-xxxV © 2003, GSI Technology ...
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Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.05 ...
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... GS8644Z36E-250 GS8644Z36E-225 GS8644Z36E-200 GS8644Z36E-166 GS8644Z36E-150 GS8644Z36E-133 GS8644Z18E-250I GS8644Z18E-225I GS8644Z18E-200I GS8644Z18E-166I GS8644Z18E-150I GS8644Z18E-133I GS8644Z36E-250I GS8644Z36E-225I GS8644Z36E-200I GS8644Z36E-166I GS8644Z36E-150I GS8644Z36E-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644Z18B-150IB. ...
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... GS8644Z36E-250V GS8644Z36E-225V GS8644Z36E-200V GS8644Z36E-166V GS8644Z36E-150V GS8644Z36E-133V GS8644Z18E-250IV GS8644Z18E-225IV GS8644Z18E-200IV GS8644Z18E-166IV GS8644Z18E-150IV GS8644Z18E-133IV GS8644Z36E-250IV GS8644Z36E-225IV GS8644Z36E-200IV GS8644Z36E-166IV GS8644Z36E-150IV GS8644Z36E-133IV Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644Z18B-150IB. ...
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... Sync SRAM Datasheet Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New 8644ZVxx_r1 8644ZVxx_r1; 8644ZVxx_r1_01 8644ZVxx_r1_01; 8644ZVxx_r1_02 8644ZVxx_r1_02; 8644ZVxx_r1_03 8644ZVxx_r1_03; 8644ZVxx_r1_04 8644ZVxx_r1_04; 8644Zxx_V_r1_05 Rev: 1.05 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • ...