HYS64V4120GU-10 SIEMENS [Siemens Semiconductor Group], HYS64V4120GU-10 Datasheet
HYS64V4120GU-10
Related parts for HYS64V4120GU-10
HYS64V4120GU-10 Summary of contents
Page 1
... Serial Presence Detect with E • Utilizes SDRAMs in TSOPII-44 packages • 4096 refresh cycles every 64 ms • Gold contact pad • Card Size: 133, 29. 4,00 mm for HYS64(72)V4120GU • Semiconductor Group -10 66 MHz @ CL=2 100 MHz @ CL CL CL=3 2 PROM 1 1 HYS64V4120GU-10 HYS72V4120GU-10 2.98 ...
Page 2
... The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint. This SDRAM module is available with a board-height of 1,15“ . Ordering Information Type ...
Page 3
... A10 VCC 82 41 VCC 83 42 CLK0 84 Note : Pinnames in brackets are for the x72 ECC versions Semiconductor Group 4M x 64/72 SDRAM-Module Symbol PIN # Symbol VSS 85 VSS DU 86 DQ32 CS2 87 DQ33 DQMB2 88 DQ34 DQMB3 89 DQ35 DU 90 VCC VCC 91 ...
Page 4
... CKE0 D0 - D7,(D16) VDD 10k CKE1 D9 - D15,(D17) Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted. Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4120GU) Semiconductor Group CS CS DQM DQMB4 DQ0-DQ7 ...
Page 5
... I( MHz Symbol ICL HYS64(72)V4120GU- 64/72 SDRAM-Module Limit Values min. max. 2.0 Vcc+0.3 IH – 0.5 0.8 IL 2.4 – OH – 0.4 OL – – Limit Values Unit max. max. (x64) (x72 ...
Page 6
... Down Mode Icc3NS Burst Operating Icc4 Current Auto (CBR) Refresh Icc5 Current Self Refresh Current Icc6 Semiconductor Group 4M x 64/72 SDRAM-Module VCC = 3.3V a Test Condition Burst length = 4, CL=3 trc>=trc(min.), tck>=tck(min.), Io bank interleave operation CKE<=VIL(max), tck>=tck(min.) CKE<=VIL(max), tck=infinite CKE> ...
Page 7
... CL t CKS t CKH t CKSP t CKSR RCD RAS RRD 7 HYS64(72)V4120GU- 64/72 SDRAM-Module Limit Values Unit Note -10 max – 100 MHz – 66 MHz – 33 MHz 5 – – – – ...
Page 8
... CAS Latency = 2 CAS Latency = 1 DQM Data Out Disable Latency Write Cycle Data In Setup Time Data In Hold Time Data input to Precharge Data In to Active/refresh DQM Write Mask Latency Semiconductor Group HYS64(72)V4120GU- 64/72 SDRAM-Module Limit Values Symbol -10 min max t 1 – CCD t 2Clk – ...
Page 9
... The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’ s) are stable during tRC(min.). ...
Page 10
... Minimum Row Precharge Time 28 Minimum Row Active to Row Active delay tRRD Semiconductor Group 2 PROM - is assembled onto the module. Information about the module 2 PROM device during module production using a serial presence Description SPD Entry Value & full page CAS latency = 1, 2 ...
Page 11
... SPD-Table (cont’ Byte# 29 Minimum RAS to CAS delay tRCD 30 Minimum Ras pulse width tRAS 31 Module Bank Density (per bank) 32-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 64- Manufactures’ s information (optional) 127 (FFh if not used) 128+ Unused storage locations ...