HYS64V4120GU-10 SIEMENS [Siemens Semiconductor Group], HYS64V4120GU-10 Datasheet - Page 10

• Manufacturer Part Number: HYS64V4120GU-10
• Description: 3.3V 4M x 64-Bit 2 BANK SDRAM Module 3.3V 4M x 72-Bit 2 BANK SDRAM Module
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

A serial presence detect storage device - E
configuration, speed, etc. is written into the E
detect protocol ( I
PD-Table:
Semiconductor Group
Byte#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
1
2
3
4
5
6
7
8
9
2
C synchronous 2-wire bus)
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’ d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back ran-
dom column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
SDRAM Device Attributes :General
SDRAM Cycle Time at CL = 2
SDRAM Access Time from Clock at CL = 2
SDRAM Cylce Time at CL = 1
SDRAM Access Time from Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active delay
tRRD
(for x8 SDRAM)
Description
2
PROM - is assembled onto the module. Information about the module
2
PROM device during module production using a serial presence
10
1, 2, 4, 8 & full page
CAS latency = 1, 2
SPD Entry Value
non buffered/non
Write latency = 0
Vcc tol +/- 10%
CS latency = 0
Self-Refresh,
t
none / ECC
4M x 64/72 SDRAM-Module
ccd
SDRAM
10.0 ns
n/a / x8
15.0 ns
64 / 72
LVTTL
8.0 ns
15.6 s
9.0 ns
30 ns
27 ns
30 ns
20 ns
= 1 CLK
& 3
128
256
reg.
11
x8
9
2
0
2
HYS64(72)V4120GU-10
x64
-10
0B
A0
80
8F
F0
6C
1E
80
08
04
09
02
40
00
01
00
80
08
00
01
02
07
01
01
00
06
90
78
14
Hex
x72
-10
0B
A0
8F
6C
1E
80
08
04
09
02
48
00
01
80
02
80
08
08
01
02
07
01
01
00
06
F0
90
78
14