EDD10163BBH-5BLS-F ELPIDA [Elpida Memory], EDD10163BBH-5BLS-F Datasheet
EDD10163BBH-5BLS-F
Available stocks
Related parts for EDD10163BBH-5BLS-F
EDD10163BBH-5BLS-F Summary of contents
Page 1
... PRELIMINARY DATA SHEET 1G bits DDR Mobile RAM WTR (Wide Temperature Range), Low Power Function EDD10163BBH-LS (64M words 16 bits) Specifications Density: 1G bits Organization: 16M words 16 bits 4 banks Package: 60-ball FBGA Lead-free (RoHS compliant) and Halogen-free Power supply: VDD, VDDQ 1.7V to 1.95V Data rate: 400Mbps/333Mbps (max.) ...
Page 2
... Ordering Information Die Part number revision EDD10163BBH-5BLS-F B EDD10163BBH-6ELS-F Part Number Elpida Memory Type D: Monolithic Device Product Family D: DDR Mobile RAM Density / Bank 10: 1Gb / 4-bank Organization 16: x16 Power Supply, Interface 3: 1.8V, LVCMOS, w/ Low Power Function Preliminary Data Sheet E1436E30 (Ver. 3.0) ...
Page 3
... BA0 A8 A10 (Top View) Pin name CK /CK CKE VDD VSS VDDQ VSSQ NC 3 EDD10163BBH-LS 9 VDD VSSQ VDDQ VSSQ VDDQ VDD /RAS BA1 A1 VDD Function Clock input Differential clock input Clock enable Power for internal circuit Ground for internal circuit ...
Page 4
... CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................12 Pin Function.................................................................................................................................................13 Command Operation ...................................................................................................................................15 Simplified State Diagram .............................................................................................................................21 Operation of the DDR Mobile RAM .............................................................................................................22 Timing Waveforms.......................................................................................................................................46 Package Drawing ........................................................................................................................................57 Recommended Soldering Conditions..........................................................................................................58 Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS 4 ...
Page 5
... VDDQ 0.6 VID (DC) 0.4 VDDQ — VID (AC) 0.6 VDDQ — 0.7 VDDQ — VILD (DC) 0.3 — VIHD (AC) 0.8 VDDQ — VILD (AC) 0.3 — 5ns). 5ns). VDDQ and must track variations in the DC level of the same. 5 EDD10163BBH-LS Unit Note max. Unit Notes 1. VDDQ + 0.3 V 0.2 VDDQ V VDDQ + 0.3 V ...
Page 6
... Address inputs are SWITCHING, 50% data change each burst transfer CKE = H, tCK = tCK (min.), tRFC = tRFC (min.), 120 mA Address and control inputs are SWITCHING; Data bus inputs are STABLE Address and control inputs are STABLE Data bus inputs are STABLE 6 EDD10163BBH-LS Notes ...
Page 7
... All other input-only pins 1.5 — CK, /CK — — All other input-only pins — — DQ, DM, DQS 2.0 — DQ, DM, DQS — — 100MHz, VOUT = VDDQ/2, 7 EDD10163BBH-LS Condition Notes +40 C CKE = L +40 C < TA +70 C CKE = L +70 C < TA +85 C CKE = L Test condition Notes 0 VIN ...
Page 8
... Active to Read/Write delay tRCD Precharge to active command period tRP Column address to column address tCCD delay Active to active command period tRRD Write recovery time tWR Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS -5BLS -6ELS min. max. min. max. 5.0 — 6.0 — 0.45 0.55 0.45 ...
Page 9
... Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for tRP. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer. Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS -5BLS -6ELS min. max. ...
Page 10
... Test Condition (Wave form and Timing Reference) Preliminary Data Sheet E1436E30 (Ver. 3.0) Symbol Value VIH (AC) 0.8 VDDQ VIL (AC) 0.2 VDDQ VID (AC) 1.4 VIX (AC) VDDQ/2 with VDD=VDDQ SLEW VID VIX T VDDQ Output Load 10 EDD10163BBH-LS Unit Note V/ VIH VIL ( slew rate = T ...
Page 11
... BL BL/2 BL EDD10163BBH-LS 7.5ns min. max. Unit 3 + BL/2 tCK BL/2 tCK 2 + BL/2 tCK 3 tCK 3 tCK 3 + BL/2 tCK 3 tCK 1 tCK 2 tCK 0 tCK 2 tCK 16 tCK 11 tCK 1 tCK 1 tCK 2 tCK ...
Page 12
... Block Diagram CK /CK CKE Address, BA0, BA1 Mode register /CS /RAS /CAS /WE Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS Bank 3 Bank 2 Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit ...
Page 13
... Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Preliminary Data Sheet E1436E30 (Ver. 3.0) Address (A0 to A13) Organization Row address 16 bits AX0 to AX13 BA1 EDD10163BBH-LS Column address AY0 to AY9 ...
Page 14
... VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDD must be equal to VDDQ. Preliminary Data Sheet E1436E30 (Ver. 3.0) DQS Data mask LDQS LDM UDQS UDM 14 EDD10163BBH-LS DQs DQ0 to DQ7 DQ8 to DQ15 ...
Page 15
... L H PRE PALL REF SELF MRS EMRS EDD10163BBH-LS BA1 BA0 AP Address ...
Page 16
... The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins in the mode register set cycle. For details, refer to "Mode register and extended mode register set". Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS BA1 L L ...
Page 17
... BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACT BA, A10 PRE, PALL DESL NOP BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACT BA, A10 PRE, PALL 17 EDD10163BBH-LS Operation NOP NOP 11 ILLEGAL* 11 ILLEGAL* 11 ILLEGAL* 11 ILLEGAL* NOP ILLEGAL NOP NOP NOP 11 ILLEGAL* 11 ILLEGAL* ...
Page 18
... BA, RA ACT BA, A10 PRE, PALL DESL NOP BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACT BA, A10 PRE/PALL 18 EDD10163BBH-LS Operation NOP NOP Burst stop Interrupting burst read operation to start new read 13 ILLEGAL* 11 ILLEGAL* Interrupting burst read operation to start pre-charge ILLEGAL NOP ...
Page 19
... DESL NOP BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRIT A BA, RA ACT BA, A10 PRE, PALL Minimum delay (Concurrent AP supported) BL/2 CL (rounded up)+ (BL/ (BL/2) + tWTR BL EDD10163BBH-LS Operation NOP NOP ILLEGAL 14 ILLEGAL* 14 ILLEGAL* 11, 14 ILLEGAL* 11, 14 ILLEGAL* ILLEGAL Units tCK tCK tCK tCK tCK tCK ...
Page 20
... This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle state. Power-down exit [PDEX] The DDR Mobile RAM can exit from power-down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS CKE n 1 ...
Page 21
... AUTO IDLE REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE CKE_ ROW ACTIVE BST READ WRITE READ READ WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 21 EDD10163BBH-LS Automatic sequence Manual input Deep power down exit sequence ...
Page 22
... Provide NOPs or DESL commands for at least tMRD time. 9. Using the MRS command, program the extended mode register for the desired operating modes. 10. Provide NOP or DESL commands for at least tMRD time. 11. The DRAM has been properly initialized and is ready for any valid command. Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS 22 ...
Page 23
... LMODE A3 Burst Type Sequential Interleave Reserved Reserved Reserved Reserved Mode Register Set 23 EDD10163BBH- Burst Length Reserved Reserved Reserved Reserved ...
Page 24
... Bank0 & Bank1 (BA1 = Bank0 (BA = BA1 = Extended Mode Register Set 24 EDD10163BBH- PASR 0 Refresh Array All banks Reserved Reserved Reserved Reserved Reserved ...
Page 25
... CK /CK CKE Command PRE Note: Assume PRE and ACT command is closing and activating same bank. Preliminary Data Sheet E1436E30 (Ver. 3.0) NOP Power-down mode Power-Down Entry and Exit NOP NOP CKE Control 25 EDD10163BBH-LS 2 Valid* NOP 2 Valid Activate command, ACT ...
Page 26
... EDD10163BBH- 10, 11, 12, 13, 14 11, 10, 13, 12, 15, 14 10, 11 14, 15, 12, 13 11, 10 15, 14, 13, 12 12, 13, 14, 15 10, 11 13, 12, 15, 14 11, 10 14, ...
Page 27
... NOP tRPRE out0 out1 tRPST out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 27 EDD10163BBH-LS out out BL: Burst length ...
Page 28
... Read Operation (/CAS Latency) WRIT NOP Column tWPRE in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in0 in1 in2 in3 in4 in5 Write Operation 28 EDD10163BBH-LS t4.5 t5 t5.5 tRPST VTT VTT out3 in6 in7 in in in6 in7 14 15 BL: Burst length ...
Page 29
... The BST command is also supported for the burst write operation. No data will be written in subsequent cycles. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK Command READ DQS DQ Burst Stop during a Read Operation Preliminary Data Sheet E1436E30 (Ver. 3.0) t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ out0 out1 29 EDD10163BBH-LS t4.5 t5 t5.5 CL: /CAS latency ...
Page 30
... Note: Internal auto-precharge starts at the timing indicated by " Preliminary Data Sheet E1436E30 (Ver. 3.0) tRAS (min) tRP (min) BL/2 (= tRPD) READA NOP tAC,tDQSCK out0 ". Read with auto precharge NOP WL + BL/2 + tWR (= tWPD) in1 in2 in3 in4 ". Burst Write ( EDD10163BBH-LS ACT out1 out2 out3 tRP ACT ...
Page 31
... ACT command. tRCD after the ACT command, the consecutive read command can be issued. tn tn+1 tn+2 tn+3 READ READ out out A0 A1 Column = A Column = B Read Read Column = A Dout 31 EDD10163BBH-LS tn+4 tn+5 tn+6 NOP out out out out Column = B Dout Bank0 ...
Page 32
... READ to READ Command Interval (different bank)* Note Preliminary Data Sheet E1436E30 (Ver. 3.0) tn tn+1 tn+2 tn+3 READ READ NOP Column A Column B out A0 Column = A Column = B Read Read Bank0 Dout Bank0 Bank3 Read Read 32 EDD10163BBH-LS tn+4 tn+5 tn+6 NOP out out out out out Bank3 Dout ...
Page 33
... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 33 EDD10163BBH-LS tn+5 tn+6 NOP Bank0 ...
Page 34
... NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E1436E30 (Ver. 3.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 34 EDD10163BBH-LS tn+3 tn+4 tn+5 NOP Bank0, 3 ...
Page 35
... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued NOP WRIT tBSTZ (= CL) out0 out1 in0 in1 OUTPUT READ to WRITE Command Interval 35 EDD10163BBH- NOP in2 in3 INPUT ...
Page 36
... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued READ tWTR* in2 in3 WRITE to READ Command Interval 36 EDD10163BBH- NOP out0 out1 out2 OUTPUT ...
Page 37
... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP in2 out0 out1 out2 out3 37 EDD10163BBH- High-Z High ...
Page 38
... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 4 clock cycle] Preliminary Data Sheet E1436E30 (Ver. 3. NOP in2 in3 out0 out1 out2 out3 READ tWTR* in3 38 EDD10163BBH- High-Z High NOP out0 out1 out2 out3 ...
Page 39
... DQS Data will be written [WRITE to BST delay = 2 clock cycle] Preliminary Data Sheet E1436E30 (Ver. 3. in1 Following data will not be written BST NOP in2 in3 Following data will not be written. 39 EDD10163BBH- NOP longer longer ...
Page 40
... CK /CK Command WRIT NOP DM DQ in0 in1 DQS Data will be written [WRITE to BST delay = 3 clock cycle] Preliminary Data Sheet E1436E30 (Ver. 3. BST in2 in3 in4 in5 Following data will not be written. 40 EDD10163BBH- NOP longer ...
Page 41
... Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Preliminary Data Sheet E1436E30 (Ver. 3. PRE/ NOP PALL out0 out1 out2 out3 PRE/PALL NOP out0 out1 tHZP 41 EDD10163BBH- High-Z High-Z ...
Page 42
... The minimum interval tWPD is necessary between the write command and the precharge command /CK Command WRIT DM DQS DQ in0 in1 WRITE to PRECHARGE Command Interval (same bank) ( Preliminary Data Sheet E1436E30 (Ver. 3. PRE/PALL NOP tWPD tWR in2 in3 Last data input 42 EDD10163BBH- NOP ...
Page 43
... CK /CK Command WRIT DM DQS DQ in0 in1 Last data input WRITE to PRECHARGE Command Interval (same bank) ( mask data) Preliminary Data Sheet E1436E30 (Ver. 3. PRE/PALL NOP tWPD tWR in2 in3 Data masked 43 EDD10163BBH- NOP ...
Page 44
... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD Mode Register Set to Bank Active 44 EDD10163BBH-LS NOP ACT NOP ROW: 0 Bank0 Active NOP ...
Page 45
... When DM is set to high, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Preliminary Data Sheet E1436E30 (Ver. 3. Mask Mask Write mask latency = 0 DM Control 45 EDD10163BBH- ...
Page 46
... Command and Addresses Input Timing Definition CK /CK Command (/RAS, /CAS, /WE, /CS) Address Read Timing Definition (1) CK /CK Command READ High-Z DQ (Output) High-Z DQS Preliminary Data Sheet E1436E30 (Ver. 3.0) tIS tIH tIS tIH tLZ (min.) tLZ (min.) 46 EDD10163BBH-LS = Don't care tHZ (max.) High-Z High ...
Page 47
... Write Timing Definition tCK /CK CK tDQSS tWPRES DQS tWPRE DQ (Din) DM Preliminary Data Sheet E1436E30 (Ver. 3.0) tDQSCK tDSC tQH tDQSQ tDQSCK tDQSQ tDSS tDSH tDSC tDQSL tDQSH tDIPW tDS tDH tDS tDH tDIPW 47 EDD10163BBH-LS tQH tQHS Invalid tDSS tWPST tDIPW Don't care ...
Page 48
... Command is necessary Preliminary Data Sheet E1436E30 (Ver. 3.0) 2 refresh cycles are necessary tRP tRFC tRFC Auto-Refresh Auto-Refresh Command Command is necessary is necessary 48 EDD10163BBH-LS Address key Address key tMRD tMRD Mode Extended Activate Register Set Mode Command Command Register Set is necessary Command ...
Page 49
... Bank 0 Bank 0 Bank 0 Bank 0 Read Read Precharge Precharge 49 EDD10163BBH-LS tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = Don't care ...
Page 50
... Bank 0 Precharge 50 EDD10163BBH-LS tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH Bank0 Access = Don't care ...
Page 51
... Bank 3 Read Precharge Active T10 R:b C Read Write tRWD tWRD Bank 3 Bank 3 Active Write 51 EDD10163BBH-LS T10 T11 T12 T13 T14 T15 Don't care T11 Tn Tn+1 Tn+2 Tn+3 Tn+4 C:b'' b’’ Read Bank 3 Read Read cycle Don't care ...
Page 52
... Auto-Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM High-Z DQS High-Z DQ tRP Precharge Auto If needed Refresh Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH- tRFC Bank 0 Bank 0 Active Read Don't care ...
Page 53
... Self-Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ tRP Precharge Self refresh If needed entry Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS tIH CKE = low R: b tSREX Bank 0 Self refresh Active exit Bank 0 Read Don't care ...
Page 54
... Power-Down Entry and Exit /CK CK CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ tRP Precharge If needed Preliminary Data Sheet E1436E30 (Ver. 3. CKE = low tCKE R: b tPDEX tPDEN Power down Power Bank 0 entry down Active exit 54 EDD10163BBH- Bank 0 Read Don't care ...
Page 55
... Deep Power-Down Entry /CK CKE /CS /RAS /CAS /WE BA0 BA1 A10 Address DM High-Z DQ tRP Precharge Deep All Banks Power Down Command Entry Preliminary Data Sheet E1436E30 (Ver. 3.0) Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 55 EDD10163BBH-LS Tn+6 = Don't care ...
Page 56
... Note: The sequence of auto-refresh, mode register programming and extended mode register programming above may be transposed. Preliminary Data Sheet E1436E30 (Ver. 3.0) tMRD tMRD Address key tRFC Extended CBR (Auto) CBR (Auto) Mode Refresh Refresh Register Set Command Command Command is necessary is necessary is necessary 56 EDD10163BBH-LS 2 refresh cycles are necessary tRFC Activate Command = Don't care ...
Page 57
... Package Drawing 60-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) NDEX MARK I 0. INDEX MARK Preliminary Data Sheet E1436E30 (Ver. 3.0) 9.00 ± 0.10 0. 0.15 0.20 S 1.00 max. S 0.35 ± 0.05 A 60-φ0.45 ± 0.05 1.6 0.8 6.4 ECA-TS2-0302-01 57 EDD10163BBH-LS Unit: mm φ0. ...
Page 58
... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD10163BBH. Type of Surface Mount Device EDD10163BBH: 60-ball FBGA < Lead free (Sn-Ag-Cu) > Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS 58 ...
Page 59
... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH-LS 59 CME0107 ...
Page 60
... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E1436E30 (Ver. 3.0) EDD10163BBH- ...