EDD1216AATA-5 ELPIDA [Elpida Memory], EDD1216AATA-5 Datasheet

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... DDR SDRAM EDD1216AATA-5 (8M words 16 bits, DDR400) Description The EDD1216AATA is a 128M bits Double Data Rate (DDR) SDRAM organized as 2,097,154 words 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high- speed data transfer is realized by the 2 bits prefetch- pipelined architecture ...

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... Organization 16: x16 Power Supply, Interface A: 2.5V, SSTL_2 Die Rev. Data Sheet E0443E40 (Ver. 4.0) Internal Data rate JEDEC speed bin bits) banks Mbps (max.) (CL-tRCD-tRP) DDR400B (3-3-3) 4 400 DDR400C (3-4-4) 2 EDD1216AATA-5 Package 66-pin Plastic TSOP (II) Environment Code E: Lead Free Speed 5B: DDR400B (3-3-3) 5C: DDR400C (3-4-4) Package TA: TSOP (II) ...

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... CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram .............................................................................................................................................10 Pin Function.................................................................................................................................................11 Command Operation ...................................................................................................................................13 Simplified State Diagram .............................................................................................................................20 Operation of the DDR SDRAM ....................................................................................................................21 Timing Waveforms.......................................................................................................................................39 Package Drawing ........................................................................................................................................45 Recommended Soldering Conditions..........................................................................................................46 Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 3 ...

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... +70 Tstg –55 to +125 min. typ. 2.5 2 0.49 VDDQ 0.50 VDDQ VREF – 0.04 VREF VREF + 0.15 — –0.3 — –0.3 — 0.5 VDDQ 0.2V 0.5 VDDQ 0.36 — 4 EDD1216AATA-5 Unit Note max. Unit Notes 2 0.51 VDDQ V VREF + 0.04 V VDDQ + 0 VREF – 0. VDDQ + 0 ...

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... Input ≤ 0.2 V 350 max. Unit Test condition 2 µA VDD ≥ VIN ≥ VSS 5 µA VDDQ ≥ VOUT ≥ VSS — mA VOUT = 1.95V — mA VOUT = 0.35V 5 EDD1216AATA-5 Notes Note ...

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... EDD1216AATA-5 max. Unit Notes VOUT = 0.2V, max. Unit Notes 0.55 tCK 0.55 tCK — tCK 0 ...

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... For each of the terms above, if not already an integer, round to the next highest integer. Example: For –5C Speed tCK = 5ns, tWR = 15ns and tRP= 18ns, tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4) tDAL = 7 clocks Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 -5B -5C min. max. min. ...

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... VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF 0.31 VID (AC) 0.62 VIX (AC) VREF SLEW 1 tCK tCL tCH VIX VDD VIH VREF VIL VSS t SLEW = (VIH (AC) – VIL (AC))/ t VTT 30pF Input Waveforms and Output Load 8 EDD1216AATA-5 Unit V/ns VDD VREF VSS ...

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... DM to data in latency Mode register set command cycle time Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 Number of clock cycle 5ns Symbol min. max. — tWPD 4 + BL/2 — ...

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... Data Sheet E0443E40 (Ver. 4.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit counter Latch circuit DLL CK, /CK Input & Output buffer DQ 10 EDD1216AATA-5 Bank 3 Bank 2 DQS DM ...

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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 Column address AY0 to AY8 BA1 ...

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... VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM 12 ...

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... L H PRE PALL REF SELF MRS EMRS EDD1216AATA-5 BA1 BA0 AP Address ...

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... Power down Power down exit (PDEX) Remark: H: VIH. L: VIL. : VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 BA1 CKE n – 1 ...

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... NOP NOP NOP BST ILLEGAL BA, CA, A10 READ/READA Starting read operation Read/READA BA, CA, A10 WRIT/WRITA Starting write operation BA, RA ACT ILLEGAL* BA, A10 PRE, PALL Pre-charge ILLEGAL 15 EDD1216AATA-5 Next state ldle ldle 11 — 11 — 11 — 11 — ldle — ldle ldle 11 — 11 — ...

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... NOP NOP BST ILLEGAL BA, CA, A10 READ/READA Starting read operation. Read/ReadA Starting new write BA, CA, A10 WRIT/WRITA operation. BA, RA ACT ILLEGAL* BA, A10 PRE/PALL ILLEGAL* ILLEGAL 16 EDD1216AATA-5 Next state Active Active Active Active 13 — 11 — Precharging — Precharging Precharging — 14 — 14 — ...

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... ILLEGAL* BA, CA, A10 WRIT/WRIT A ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 PRE, PALL ILLEGAL* ILLEGAL Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL EDD1216AATA-5 Next state Precharging Precharging — 14 — 14 — 11, 14 — 11, 14 — — Units tCK tCK tCK tCK tCK tCK ...

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... OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table H Refer to operations in Function Truth Table L H Self refresh L L OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 18 EDD1216AATA-5 Notes Idle ...

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... DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 15.6 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 19 ...

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... Data Sheet E0443E40 (Ver. 4.0) SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE REFRESH CKE CKE_ IDLE ACTIVE POWER CKE_ DOWN CKE ROW ACTIVE BST READ WRITE READ Read WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 20 EDD1216AATA-5 ...

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... REF REF RFC 200 cycles (min LMODE BT A3 Burst Type Sequential 1 Interleave 21 EDD1216AATA-5 (9) Any MRS command t 2 cycles (min.) RFC Disable DLL reset with A8 = Low Burst Length BT=0 BT ...

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... EDD1216AATA DLL A0 DLL Control 0 DLL Enable 1 DLL Disable Interleave ...

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... Data Sheet E0443E40 (Ver. 4.0) tCK + tAC (ns) after the clock rising READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 23 EDD1216AATA-5 t11 t9 t10 tRPST BL: Burst length ...

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... NOP tRPRE tAC,tDQSCK out0 out1 Read Operation (/CAS Latency) tn tn+0.5 tn+1 tn+2 tn+3 WRITE NOP Column tWPRE tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 Write Operation 24 EDD1216AATA-5 t4.5 t5 t5.5 tRPST VTT VTT out2 out3 tn+4 tn+5 in6 in7 BL: Burst length ...

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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS Burst Stop during a Read Operation Data Sheet E0443E40 (Ver. 4.0) t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ out0 out1 25 EDD1216AATA-5 t4.5 t5 t5.5 3 cycles CL: /CAS latency ...

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... Note: Internal auto-precharge starts at the timing indicated by " Data Sheet E0443E40 (Ver. 4.0) Refer to ‘Function truth table and related tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 in3 in4 ". Burst Write ( EDD1216AATA-5 tRP (min) ACT out3 tRP ACT ...

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... ACT command. tRCD after the ACT command, the consecutive read command can be issued NOP READ Column B out out out Column = A Column = B Read Read Column = A Dout 27 EDD1216AATA-5 t9 t10 t11 out out out Column = B Dout Bank0 ...

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... Active READ to READ Command Interval (different bank) Data Sheet E0443E40 (Ver. 4. READ READ NOP Column A Column B Column = A Column = B Read Read Bank0 Bank3 Read Read 28 EDD1216AATA t10 t11 NOP out out out out out out Bank0 Bank3 ...

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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 29 EDD1216AATA-5 tn+5 tn+6 NOP Bank0 ...

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... ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Data Sheet E0443E40 (Ver. 4.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 30 EDD1216AATA-5 tn+3 tn+4 tn+5 NOP Bank0, 3 ...

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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued WRIT NOP tBSTZ (= CL) out0 out1 in0 in1 OUTPUT READ to WRITE Command Interval 31 EDD1216AATA NOP in2 in3 INPUT ...

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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued READ tWTR* in2 in3 WRITE to READ Command Interval 32 EDD1216AATA NOP out2 out0 out1 OUTPUT ...

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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP CL=3 out0 out1 out2 out3 in2 33 EDD1216AATA High-Z High ...

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... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 3 clock cycle] Data Sheet E0443E40 (Ver. 4. NOP CL=3 in2 in3 out0 out1 out2 out3 READ CL=3 tWTR* in2 in3 34 EDD1216AATA High-Z High NOP out0 out1 out2 out3 ...

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... NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Data Sheet E0443E40 (Ver. 4. PRE/ NOP PALL out0 out1 out2 out3 PRE/PALL NOP out0 out1 tHZP 35 EDD1216AATA High-Z High-Z ...

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... Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Data Sheet E0443E40 (Ver. 4. NOP tWPD tWR in2 in3 Last data input PRE/PALL NOP tWR in2 in3 Data masked 36 EDD1216AATA PRE/PALL NOP t6 t7 NOP ...

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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD 37 EDD1216AATA-5 NOP ACT NOP ROW: 0 Bank0 Active NOP ...

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... By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Data Sheet E0443E40 (Ver. 4. Mask Mask Write mask latency = 0 DM Control 38 EDD1216AATA ...

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... Data Sheet E0443E40 (Ver. 4.0) tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW tDH tDH tDIPW 39 EDD1216AATA-5 VREF VREF tDQSCK tRPST tDQSQ tQH tAC tHZ tDQSQ tQH tDSS VREF tWPST VREF VREF tDIPW ...

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... Bank 0 Bank 0 Bank 0 Read Read Precharge 40 EDD1216AATA-5 tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = VIH or VIL ...

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... Data Sheet E0443E40 (Ver. 4.0) tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 41 EDD1216AATA-5 tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...

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... Data Sheet E0443E40 (Ver. 4. tMRD Bank 3 Bank 3 Bank 3 Read Precharge Active R:b C tRWD Bank 3 Bank 3 Active Write 42 EDD1216AATA VIH or VIL C:b'' b’’ tWRD Bank 3 Read Read cycle =VIH or VIL ...

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... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Data Sheet E0443E40 (Ver. 4. High-Z tRFC Auto Bank 0 Refresh Active 43 EDD1216AATA Bank 0 Read VIH or VIL ...

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... Self Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Data Sheet E0443E40 (Ver. 4.0) tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active 44 EDD1216AATA Bank 0 Read VIH or VIL ...

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... PIN 0.65 0.17 to 0.32 0. 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. Data Sheet E0443E40 (Ver. 4. 8° 45 EDD1216AATA-5 Unit: mm 0.80 Nom 0.25 +0.15 0.60 −0.20 ECA-TS2-0143-01 ...

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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD1216AATA. Type of Surface Mount Device EDD1216AATA: 66-pin Plastic TSOP (II) < Lead free(Sn-Bi) > Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 46 ...

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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 47 CME0107 ...

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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Data Sheet E0443E40 (Ver. 4.0) EDD1216AATA-5 48 M01E0107 ...