EDD2504AKTA-6B ELPIDA [Elpida Memory], EDD2504AKTA-6B Datasheet
EDD2504AKTA-6B
Related parts for EDD2504AKTA-6B
EDD2504AKTA-6B Summary of contents
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... DDR SDRAM EDD2504AKTA (64M words 4 bits) Description The EDD2504AK is a 256M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high- speed data transfer is realized by the 2 bits prefetch- pipelined architecture ...
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... Ordering Information Mask Organization Part number version (words EDD2504AKTA-6B EDD2504AKTA-7A K 64M 4 EDD2504AKTA-7B Part Number Elpida Memory Type D: Monolithic Device Product Code D: DDR SDRAM Density / Bank 25: 256M / 4-bank Bit Organization 4: x4 Voltage, Interface A: 2.5V, SSTL_2 Die Rev. Package TA: TSOP (II) Speed 6B: DDR333B (2.5-3-3) 7A: DDR266A (2-3-3) 7B: DDR266B (2.5-3-3) Data Sheet E0457E10 (Ver ...
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... CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram .............................................................................................................................................10 Pin Function.................................................................................................................................................11 Command Operation ...................................................................................................................................13 Simplified State Diagram .............................................................................................................................20 Operation of the DDR SDRAM ....................................................................................................................21 Timing Waveforms.......................................................................................................................................40 Package Drawing ........................................................................................................................................46 Recommended Soldering Conditions ..........................................................................................................47 Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA 3 ...
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... +70 Tstg –55 to +125 min. typ. 2.3 2 0.49 VDDQ 0.50 VDDQ VREF – 0.04 VREF VREF + 0.15 — –0.3 — –0.3 — 0.5 VDDQ 0.2V 0.5 VDDQ 0.36 — 4 EDD2504AKTA Unit Note max. Unit Notes 2 0.51 VDDQ V VREF + 0.04 V VDDQ + 0 VREF – 0. VDDQ + 0 ...
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... -7A, -7B 270 max. Unit Test condition 2 µA VDD ≥ VIN ≥ VSS 5 µA VDDQ ≥ VOUT ≥ VSS — mA VOUT = 1.95V — mA VOUT = 0.35V 5 EDD2504AKTA Notes Notes ...
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... EDD2504AKTA max. Unit Notes VOUT = 0.2V, -7B min. max. Unit Notes 7 0.45 0.55 tCK 0.45 0.55 tCK min — ...
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... EDD2504AKTA -7B min. max. Unit Notes 0.9 — 0.9 — 2.2 — — tCK 45 120000 ns 67.5 — — — ...
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... VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF 0.31 VID (AC) 0.62 VIX (AC) VREF SLEW 1 tCK tCL tCH VIX VDD VIH VREF VIL VSS t SLEW = (VIH (AC) – VIL (AC))/ t VTT 30pF Input Waveforms and Output Load 8 EDD2504AKTA Unit V/ns VDD VREF VSS ...
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... EDD2504AKTA max. Unit — tCK — tCK — tCK — tCK — tCK 2 tCK 2.5 tCK — tCK — tCK 2 tCK 2.5 tCK 1 tCK — tCK ...
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... Data Sheet E0457E10 (Ver. 1.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit counter Latch circuit DLL Input & Output buffer CK, / EDD2504AKTA Bank 3 Bank 2 DQS DM ...
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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA Column address AY0 to AY9, AY11 BA1 ...
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... DQS provides the read data strobe (as output) and the write data strobe (as input). VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA 12 ...
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... PRE PALL REF SELF MRS EMRS EDD2504AKTA Address ...
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... The CKE level must be kept for 1 CK cycle at least. Data Sheet E0457E10 (Ver. 1.0) BA1 CKE n – /CS /RAS /CAS / EDD2504AKTA Address Notes 2 2 ...
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... NOP NOP NOP BST ILLEGAL BA, CA, A10 READ/READA Starting read operation Read/READA BA, CA, A10 WRIT/WRITA Starting write operation BA, RA ACT ILLEGAL* BA, A10 PRE, PALL Pre-charge ILLEGAL 15 EDD2504AKTA Next state ldle ldle 11 — 11 — 11 — 11 — ldle — ldle ldle 11 — 11 — ...
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... NOP NOP BST ILLEGAL BA, CA, A10 READ/READA Starting read operation. Read/ReadA Starting new write BA, CA, A10 WRIT/WRITA operation. BA, RA ACT ILLEGAL* BA, A10 PRE/PALL ILLEGAL* ILLEGAL 16 EDD2504AKTA Next state Active Active Active Active 13 — 11 — Precharging — Precharging Precharging — 14 — 14 — ...
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... ILLEGAL* BA, CA, A10 WRIT/WRIT A ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 PRE, PALL ILLEGAL* ILLEGAL Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL EDD2504AKTA Next state Precharging Precharging — 14 — 14 — 11, 14 — 11, 14 — — Units tCK tCK tCK tCK tCK tCK ...
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... OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table H Refer to operations in Function Truth Table L H Self refresh L L OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 18 EDD2504AKTA Notes Idle ...
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... DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA 19 ...
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... Data Sheet E0457E10 (Ver. 1.0) SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE REFRESH CKE CKE_ IDLE ACTIVE POWER CKE_ DOWN CKE ROW ACTIVE BST READ WRITE READ Read WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 20 EDD2504AKTA ...
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... RFC 200 cycles (min LMODE BT A3 Burst Type Sequential 2 Interleave 21 EDD2504AKTA (9) Any MRS command t 2 cycles (min.) RFC Disable DLL reset with A8 = Low Burst Length BT=0 BT ...
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... EDD2504AKTA DLL A0 DLL Control 0 DLL Enable 1 DLL Disable Interleave ...
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... Data Sheet E0457E10 (Ver. 1.0) tCK + tAC (ns) after the clock rising READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 23 EDD2504AKTA t8 t9 tRPST BL: Burst length ...
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... Read Operation (/CAS Latency) tn tn+0.5 tn+1 tn+2 tn+3 WRITE Column tWPRE tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 Write Operation 24 EDD2504AKTA t4 t4.5 t5 t5.5 tRPST VTT VTT tRPST VTT VTT out3 tn+4 tn+5 NOP in6 in7 BL: Burst length ...
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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS DQS CL = 2.5 DQ Burst Stop during a Read Operation Data Sheet E0457E10 (Ver. 1.0) t1 t1.5 t2 t2.5 t3 t3.5 BST NOP tBSTZ 2 cycles out0 out1 tBSTZ 2.5 cycles out0 out1 25 EDD2504AKTA t4 t4.5 t5 t5.5 CL: /CAS latency ...
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... Note: Internal auto-precharge starts at the timing indicated by " Data Sheet E0457E10 (Ver. 1.0) Refer to ‘Function truth table and related tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 in3 in4 ". Burst Write ( EDD2504AKTA tRP (min) ACT out3 tRP ACT ...
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... ACT command. tRCD after the ACT command, the consecutive read command can be issued READ READ Column B out out out out Column = B Read Column = A Column = B Dout Dout 27 EDD2504AKTA NOP out out Bank0 ...
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... READ to READ Command Interval (different bank) Data Sheet E0457E10 (Ver. 1. READ READ NOP Column A Column B out out A0 A1 Column = A Column = B Read Read Bank0 Dout Bank0 Bank3 Read Read 28 EDD2504AKTA t8 t9 NOP out out out out Bank3 Dout ...
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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 29 EDD2504AKTA tn+5 tn+6 NOP Bank0 ...
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... ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Data Sheet E0457E10 (Ver. 1.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 30 EDD2504AKTA tn+3 tn+4 tn+5 NOP Bank0, 3 ...
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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued WRIT out0 out1 in0 in1 in2 in3 INPUT READ to WRITE Command Interval 31 EDD2504AKTA NOP ...
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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued NOP READ tWRD (min) tWTR* in2 in3 WRITE to READ Command Interval 32 EDD2504AKTA t5 t6 NOP out0 out1 out2 OUTPUT ...
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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP out0 out1 out2 out3 in2 33 EDD2504AKTA High-Z High CL= 2 ...
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... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 3 clock cycle] Data Sheet E0457E10 (Ver. 1. NOP CL=2 in2 in3 out0 out1 out2 out3 READ CL=2 tWTR* out0 out1 out2 out3 in2 in3 34 EDD2504AKTA High-Z High CL NOP CL= 2 ...
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... Command NOP NOP READ DQ DQS tRPD = BL/2 READ to PRECHARGE Command Interval (same bank): To output all data ( Data Sheet E0457E10 (Ver. 1. PRE/ NOP PALL out0 out1 out2 out3 PRE/ NOP PALL out0 out1 out2 out3 35 EDD2504AKTA ...
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... Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Data Sheet E0457E10 (Ver. 1. PRE/PALL NOP out0 out1 tHZP PRE/PALL NOP CL = 2.5 out0 out1 tHZP 36 EDD2504AKTA t7 t8 High-Z High High-Z High-Z ...
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... Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Data Sheet E0457E10 (Ver. 1. NOP PRE/PALL tWPD tWR in2 in3 Last data input PRE/PALL NOP tWR in2 in3 Data masked 37 EDD2504AKTA t6 t7 NOP t6 t7 NOP ...
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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD 38 EDD2504AKTA NOP ACT NOP ROW: 0 Bank0 Active NOP ...
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... DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Data Sheet E0457E10 (Ver. 1. Mask Mask Write mask latency = 0 DM Control 39 EDD2504AKTA t5 t6 ...
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... Data Sheet E0457E10 (Ver. 1.0) tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW tDH tDH tDIPW 40 EDD2504AKTA VREF VREF tDQSCK tRPST tDQSQ tQH tAC tHZ tDQSQ tQH tDSS VREF tWPST VREF VREF tDIPW ...
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... Bank 0 Bank 0 Bank 0 Read Read Precharge 41 EDD2504AKTA tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = VIH or VIL ...
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... Data Sheet E0457E10 (Ver. 1.0) tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 42 EDD2504AKTA tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...
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... Data Sheet E0457E10 (Ver. 1. tMRD Bank 3 Bank 3 Bank 3 Read Precharge Active R:b C tRWD Bank 3 Bank 3 Active Write 43 EDD2504AKTA VIH or VIL C:b'' b’’ tWRD Bank 3 Read Read cycle =VIH or VIL ...
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... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Data Sheet E0457E10 (Ver. 1. High-Z tRFC Auto Bank 0 Refresh Active 44 EDD2504AKTA Bank 0 Read VIH or VIL ...
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... Self Refresh Cycle /CK CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Data Sheet E0457E10 (Ver. 1.0) tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active 45 EDD2504AKTA Bank 0 Read VIH or VIL ...
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... A 66 PIN 0.65 0.17 to 0.32 0. 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. Data Sheet E0457E10 (Ver. 1. EDD2504AKTA Unit: mm 0.80 Nom 0.25 0.60 ± 0.15 ECA-TS2-0029-01 ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD2504AKTA. Type of Surface Mount Device EDD2504AKTA: 66-pin Plastic TSOP (II) Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA 47 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA 48 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Data Sheet E0457E10 (Ver. 1.0) EDD2504AKTA 49 M01E0107 ...