EDD2508AKTA-6BLI ELPIDA [Elpida Memory], EDD2508AKTA-6BLI Datasheet
EDD2508AKTA-6BLI
Manufacturer Part Number
EDD2508AKTA-6BLI
Description
256M bits DDR SDRAM WTR (Wide Temperature Range)
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
1.EDD2508AKTA-6BLI.pdf
(49 pages)
Description
The EDD2508AK is a 256M bits DDR SDRAM
organized as 8,388,608 words × 8 bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture.
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in standard 66-pin plastic TSOP (II).
Features
• Power supply : VDDQ = 2.5V ± 0.2V
• Data rate: 333Mbps (max.)
• Double Data Rate architecture; two data transfers per
• Bi-directional, data strobe (DQS) is transmitted
• Data inputs, outputs, and DM are synchronized with
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
• Commands entered on each positive CK edge; data
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
⎯ 7.8μs maximum average periodic refresh interval
• 2 variations of refresh
⎯ Auto refresh
⎯ Self refresh
• Ambient temperature range: –40 to +85°C
Document No. E0434E10 (Ver. 1.0)
Date Published November 2003 (K) Japan
URL: http://www.elpida.com
clock cycle
/received with data, to be used in capturing data at
the receiver
DQS
aligned with data for WRITEs
transitions
and data mask referenced to both edges of DQS
Data strobe (DQS) both for read and
: VDD = 2.5V ± 0.2V
WTR (Wide Temperature Range)
EDD2508AKTA-LI (32M words × 8 bits)
256M bits DDR SDRAM
This product became EOL in April, 2007.
PRELIMINARY DATA SHEET
Pin Configurations
/xxx indicates active low signal.
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
A10(AP)
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
/CAS
/RAS
VDD
DQ0
DQ1
DQ2
DQ3
VDD
VDD
/WE
BA0
BA1
/CS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66-pin Plastic TSOP(II)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
(Top view)
©Elpida Memory, Inc. 2003
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
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